SCAS892D February   2010  – July 2025 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Serial Interface
    5. 8.5 Programming
      1. 8.5.1 Data Protocol
      2. 8.5.2 Command Code Definition
      3. 8.5.3 Generic Programming Sequence
      4. 8.5.4 Byte Write Programming Sequence
      5. 8.5.5 Byte Read Programming Sequence
      6. 8.5.6 Block Write Programming Sequence
      7. 8.5.7 Block Read Programming Sequence
      8. 8.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 8.5.9 SDA and SCL Hardware Interface
  10. 9 Register Maps
    1. 9.1 SDA and SCL Configuration Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread-Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Frequency Planning
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.1 Overview

The CDCE937-Q1 and CDCEL937-Q1 devices are modular, PLL-based low-cost high-performance programmable clock synthesizers, multipliers, and dividers. The device generates up to seven output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to three independent configurable PLLs.

The CDCEx937-Q1 has separate output supply pins, VDDOUT, which is 1.8V for CDCEL937-Q1 and from 2.5V to 3.3V for CDCE937-Q1.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20 pF. Additionally, an on-chip VCXO is selectable, which allows synchronization of the output frequency to an external control signal (such as a PWM signal).

The deep M/N divider ratio allows the generation of zero ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as 27 MHz.

All PLLs support SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.

The device supports non-volatile EEPROM programming for ease-customized application. This feature is preset to a factory default configuration (see Default Device Setting). This feature can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through SDA and SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1, and S2, can be used to control various aspects of operation, including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for output-disable function.

The CDCEx937-Q1 operates in 1.8V environment. The device is characterized for operation from –40°C to 125°C.