SCAS892D February   2010  – July 2025 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Serial Interface
    5. 8.5 Programming
      1. 8.5.1 Data Protocol
      2. 8.5.2 Command Code Definition
      3. 8.5.3 Generic Programming Sequence
      4. 8.5.4 Byte Write Programming Sequence
      5. 8.5.5 Byte Read Programming Sequence
      6. 8.5.6 Block Write Programming Sequence
      7. 8.5.7 Block Read Programming Sequence
      8. 8.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 8.5.9 SDA and SCL Hardware Interface
  10. 9 Register Maps
    1. 9.1 SDA and SCL Configuration Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread-Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Frequency Planning
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

over recommended ranges of supply voltage, load, and operating ambient temperature (see Figure 8-7)
MIN NOM MAX UNIT
CLK_IN
fCLK LVCMOS clock input frequency PLL bypass mode 0 160 MHz
PLL mode 8 160
tr / tf Rise and fall time CLK signal (20% to 80%) 3 ns
dutyCLK Duty cycle CLK at VDD/2 40% 60%
SDA and SCL
fSCL SCL clock frequency Standard mode 0 100 kHz
Fast mode 0 400
tsu(START) START setup time (SCL high before SDA low) Standard mode 4.7 µs
Fast mode 0.6
th(START) START hold time (SCL low after SDA low) Standard mode 4 µs
Fast mode 0.6
tw(SCLL) SCL low-pulse duration Standard mode 4.7 µs
Fast mode 1.3
tw(SCLH) SCL high-pulse duration Standard mode 4 µs
Fast mode 0.6
th(SDA) SDA hold time (SDA valid after SCL low) Standard mode 0 3.45 µs
Fast mode 0 0.9
tsu(SDA) SDA setup time Standard mode 250 ns
Fast mode 100
tr SCL/SDA input rise time Standard mode 1000 ns
Fast mode 300
tf SCL/SDA input fall time, standard mode and fast mode 300 ns
tsu(STOP) STOP setup time Standard mode 4 µs
Fast mode 0.6
tBUS Bus free time between a STOP and START condition Standard mode 4.7 µs
Fast mode 1.3