SCAS892D February   2010  – July 2025 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Serial Interface
    5. 8.5 Programming
      1. 8.5.1 Data Protocol
      2. 8.5.2 Command Code Definition
      3. 8.5.3 Generic Programming Sequence
      4. 8.5.4 Byte Write Programming Sequence
      5. 8.5.5 Byte Read Programming Sequence
      6. 8.5.6 Block Write Programming Sequence
      7. 8.5.7 Block Read Programming Sequence
      8. 8.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 8.5.9 SDA and SCL Hardware Interface
  10. 9 Register Maps
    1. 9.1 SDA and SCL Configuration Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread-Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Frequency Planning
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.4.1 SDA and SCL Serial Interface

The CDCEx937-Q1 operates as a target device of the 2-wire serial SDA and SCL bus, compatible with the popular SMBus or I2C specification. The device operates in the standard-mode transfer (up to 100kbit/s) and fast-mode transfer (up to 400kbit/s), and supports 7-bit addressing.

The S1/SDA and S2/SCL pins of the CDC9xx are dual-function pins. In the default configuration, the pins are used as SDA and SCL serial programming interfaces. The pins can be reprogrammed as general-purpose control pins, S1 and S2, by changing the corresponding EEPROM setting, Byte 02, Bit [6].