SCAS892D February   2010  – July 2025 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Serial Interface
    5. 8.5 Programming
      1. 8.5.1 Data Protocol
      2. 8.5.2 Command Code Definition
      3. 8.5.3 Generic Programming Sequence
      4. 8.5.4 Byte Write Programming Sequence
      5. 8.5.5 Byte Read Programming Sequence
      6. 8.5.6 Block Write Programming Sequence
      7. 8.5.7 Block Read Programming Sequence
      8. 8.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 8.5.9 SDA and SCL Hardware Interface
  10. 9 Register Maps
    1. 9.1 SDA and SCL Configuration Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread-Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Frequency Planning
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

9.1 SDA and SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user-configurable. The following tables and explanations describe the programmable functions of the CDCEx937-Q1. All settings can be manually written into the device through the SDA and SCL bus, or programmed by using the TI Pro-Clock software. TI Pro-Clock software allows the user to quickly make all settings, and automatically calculates the values for optimized performance at lowest jitter.

Table 9-1 SDA and SCL Registers
ADDRESS OFFSETREGISTER DESCRIPTIONTABLE
00hGeneric Configuration registerTable 9-3
10hPLL1 Configuration registerTable 9-4
20hPLL2 Configuration registerTable 9-5
30hPLL3 Configuration registerTable 9-6

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the Control Terminal register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2 (see the Control Terminal Configuration section).

Table 9-2 Configuration Register, External Control Terminals
Y1PLL1 SETTINGSPLL2 SETTINGSPLL3 SETTINGS
EXTERNAL CONTROL PINSOUTPUT SELECTFREQ. SELECTSSC SELECTOUTPUT SELECTFREQ. SELECTSSC SELECTOUTPUT SELECTFREQ. SELECTSSC SELECTOUTPUT SELECT
S2S1S0Y1FS1SSC1Y2Y3FS2SSC2Y4Y5FS3SSC3Y6Y7
0000Y1_0FS1_0SSC1_0Y2Y3_0FS2_0SSC2_0Y4Y5_0FS3_0SSC3_0Y6Y7_0
1001Y1_1FS1_1SSC1_1Y2Y3_1FS2_1SSC2_1Y4Y5_1FS3_1SSC3_1Y6Y7_1
2010Y1_2FS1_2SSC1_2Y2Y3_2FS2_2SSC2_2Y4Y5_2FS3_2SSC3_2Y6Y7_2
3011Y1_3FS1_3SSC1_3Y2Y3_3FS2_3SSC2_3Y4Y5_3FS3_3SSC3_3Y6Y7_3
4100Y1_4FS1_4SSC1_4Y2Y3_4FS2_4SSC2_4Y4Y5_4FS3_4SSC3_4Y6Y7_4
5101Y1_5FS1_5SSC1_5Y2Y3_5FS2_5SSC2_5Y4Y5_5FS3_5SSC3_5Y6Y7_5
6110Y1_6FS1_6SSC1_6Y2Y3_6FS2_6SSC2_6Y4Y5_6FS3_6SSC3_6Y6Y7_6
7111Y1_7FS1_7SSC1_7Y2Y3_7FS2_7SSC2_7Y4Y5_7FS3_7SSC3_7Y6Y7_7
Address Offset(1)04h13h10h to 12h15h23h20h to 22h25h33h30h to 32h35h
(1) Address offset refers to the byte address in the Configuration register in the following pages.
Table 9-3 Generic Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
00h7E_ELXbDevice identification (read-only): 1 is CDCE937-Q1 (3.3V), 0 is CDCEL937-Q1 (1.8V)
6:4RIDXbRevision identification number (read only)
3:0VID1hVendor identification number (read only)
01h7–0bReserved – always write 0
6EEPIP0bEEPROM programming status:(4) (read only)0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5EELOCK0bPermanently lock EEPROM data(5)0 – EEPROM is not locked
1 – EEPROM is permanently locked
4PWDN0bDevice power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – Device active (PLL1 and all outputs are enabled)
1 – Device power down (PLL1 in power down and all outputs in 3-state)
3:2INCLK00bInput clock selection:00 – Xtal  01 – VCXO   10 – LVCMOS  11 – Reserved
1:0SLAVE_ADR01bProgrammable address bits A0 and A1 of the target receiver address
02h7M11bClock source selection for output Y1:0 – Input clock  1 – PLL1 clock
6SPICON0bOperation mode selection for pin 18/19(6)
0 – Serial programming interface SDA (pin 19) and SCL (pin 18)
1 – Control pins S1 (pin 19) and S2 (pin 18)
5:4Y1_ST111bY1-State0/1 definition
3:2Y1_ST001b00 – Device power down (all PLLs in power down and all outputs in 3-State)
01 – Y1 disabled to 3-state		10 – Y1 disabled to low
11 – Y1 enabled
1:0Pdiv1 [9:8]001h10-Bit Y1-output-divider Pdiv1:0 – divider reset and stand-by
1-to-1023 – divider value
03h7:0Pdiv1 [7:0]
04h7Y1_70bY1_ST0/Y1_ST1 state selection(7)
6Y1_60b0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
5Y1_50b
4Y1_40b
3Y1_30b
2Y1_20b
1Y1_11b
0Y1_00b
05h7:3XCSEL0AhCrystal load capacitor selection(8)00h → 0pF
01h → 1pF
02h → 2pF
:
14h-to-1Fh → 20pF
CDCE937-Q1 CDCEL937-Q1
2:00bReserved – do not write other than 0
06h7:1BCOUNT40h7-Bit byte count (defines the number of bytes sent from this device at the next Block Read transfer); all bytes must be read out to correctly finish the read cycle.)
0EEWRITE0bInitiate EEPROM write cycle(4) (9)0– No EEPROM write cycle
1 – Start EEPROM write cycle (internal configuration register is saved to the EEPROM)
07h-0Fh—0hUnused address range
(1) Writing data beyond 40h can affect device function.
(2) All data is transferred with the MSB first.
(3) Unless customer-specific setting.
(4) During EEPROM programming, no data is allowed to be sent to the device through the SDA and SCL bus until the programming sequence is completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. There is no further programming possible. Data, however can still be written through SDA and SCL bus to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM.
(6) Selection of control pins is effective only if written into the EEPROM. When written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins (SDA and SCL), and the two target receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the Control Terminal register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors must be used only to finely adjust CL by a few pFs. The value of CL can be programmed with a resolution of 1pF for a crystal load range of 0pF to 20pF. For CL > 20pF, use additional external capacitors. Also, the value of the device input capacitance must be considered, which always adds 1.5pF (6pF//2pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(9) The EEPROM WRITE bit must be sent last. This verifies that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 9-4 PLL1 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
10h7:5SSC1_7 [2:0]000bSSC1: PLL1 SSC selection (modulation amount)(4)
4:2SSC1_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC1_5 [2:1]000b
11h7SSC1_5 [0]
6:4SSC1_4 [2:0]000b
3:1SSC1_3 [2:0]000b
0SSC1_2 [2]000b
12h7:6SSC1_2 [1:0]
5:3SSC1_1 [2:0]000b
2:0SSC1_0 [2:0]000b
13h7FS1_70bFS1_x: PLL1 frequency selection(4)
6FS1_60b0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
5FS1_50b
4FS1_40b
3FS1_30b
2FS1_20b
1FS1_10b
0FS1_00b
14h7MUX11bPLL1 multiplexer:0 – PLL1
1 – PLL1 bypass (PLL1 is in power down)
6M21bOutput Y2 multiplexer:0 – Pdiv1
1 – Pdiv2
5:4M310bOutput Y3 multiplexer:00 – Pdiv1-divider
01 – Pdiv2-divider
10 – Pdiv3-divider
11 – reserved
3:2Y2Y3_ST111bY2, Y3-state0/1definition:00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
1:0Y2Y3_ST001b
15h7Y2Y3_70bY2Y3_x output state selection(4)
6Y2Y3_60b0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
5Y2Y3_50b
4Y2Y3_40b
3Y2Y3_30b
2Y2Y3_20b
1Y2Y3_11b
0Y2Y3_00b
16h7SSC1DC0bPLL1 SSC down/center selection:0 – Down    1 – Center
6:0Pdiv201h7-Bit Y2-output-divider Pdiv2:0 – Reset and stand-by   1-to-127 is divider value
17h7—0bReserved – do not write others than 0
6:0Pdiv301h7-Bit Y3-output-divider Pdiv3:0 – Reset and stand-by    1-to-127 is divider value
18h7:0PLL1_0N [11:4]004hPLL1_0: 30-bit multiplier/divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning).
19h7:4PLL1_0N [3:0]
3:0PLL1_0R [8:5]000h
1Ah7:3PLL1_0R[4:0]
2:0PLL1_0Q [5:3]10h
1Bh7:5PLL1_0Q [2:0]
4:2PLL1_0P [2:0]010b
1:0VCO1_0_RANGE00bfVCO1_0 range selection:00 – fVCO1_0 < 125MHz
01 – 125MHz ≤ fVCO1_0 < 150MHz
10 – 150MHz ≤ fVCO1_0 < 175MHz
11 – fVCO1_0 ≥ 175MHz
1Ch7:0PLL1_1N [11:4]004hPLL1_1: 30-bit multiplier/divider value for frequency fVCO1_1
(for more information, see PLL Frequency Planning).
1Dh7:4PLL1_1N [3:0]
3:0PLL1_1R [8:5]000h
1Eh7:3PLL1_1R[4:0]
2:0PLL1_1Q [5:3]10h
1Fh7:5PLL1_1Q [2:0]
4:2PLL1_1P [2:0]010b
1:0VCO1_1_RANGE00bfVCO1_1 range selection:00 – fVCO1_1 < 125MHz
01 – 125MHz ≤ fVCO1_1 < 150MHz
10 – 150MHz ≤ fVCO1_1 < 175MHz
11 – fVCO1_1 ≥ 175MHz
(1) Writing data beyond 40h can adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
Table 9-5 PLL2 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
20h7:5SSC2_7 [2:0]000bSSC2: PLL2 SSC selection (modulation amount)(4)
4:2SSC2_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC2_5 [2:1]000b
21h7SSC2_5 [0]
6:4SSC2_4 [2:0]000b
3:1SSC2_3 [2:0]000b
0SSC2_2 [2]000b
22h7:6SSC2_2 [1:0]
5:3SSC2_1 [2:0]000b
2:0SSC2_0 [2:0]000b
23h7FS2_70bFS2_x: PLL2 frequency selection(4)
6FS2_60b0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
5FS2_50b
4FS2_40b
3FS2_30b
2FS2_20b
1FS2_10b
0FS2_00b
24h7MUX21bPLL2 multiplexer:0 – PLL2
1 – PLL2 bypass (PLL2 is in power down)
6M41bOutput Y4 multiplexer:0 – Pdiv2
1 – Pdiv4
5:4M510bOutput Y5 multiplexer:00 – Pdiv2-divider
01 – Pdiv4-divider
10 – Pdiv5-divider
11 – reserved
3:2Y4Y5_ST111bY4, Y5-State0/1definition:00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State
10–Y4/Y5 disabled to low
11 – Y4/Y5 enabled
1:0Y4Y5_ST001b
25h7Y4Y5_70bY4Y5_x output state selection(4)
6Y4Y5_60b0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
5Y4Y5_50b
4Y4Y5_40b
3Y4Y5_30b
2Y4Y5_20b
1Y4Y5_11b
0Y4Y5_00b
26h7SSC2DC0bPLL2 SSC down/center selection:0 – Down
1 – Center
6:0Pdiv401h7-Bit Y4-output-divider Pdiv4:0 – Reset and stand-by   1-to-127 – Divider value
27h7—0bReserved – do not write others than 0
6:0Pdiv501h7-Bit Y5-output-divider Pdiv5:0 – Reset and stand-by    1-to-127 – Divider value
28h7:0PLL2_0N [11:4004hPLL2_0: 30-bit multiplier/divider value for frequency fVCO2_0
(for more information, see PLL Frequency Planning).
29h7:4PLL2_0N [3:0]
3:0PLL2_0R [8:5]000h
2Ah7:3PLL2_0R[4:0]
2:0PLL2_0Q [5:3]10h
2Bh7:5PLL2_0Q [2:0]
4:2PLL2_0P [2:0]010b
1:0VCO2_0_RANGE00bfVCO2_0 range selection:00 – fVCO2_0 < 125MHz
01 – 125MHz ≤ fVCO2_0 < 150MHz
10 – 150MHz ≤ fVCO2_0 < 175MHz
11 – fVCO2_0 ≥ 175MHz
2Ch7:0PLL2_1N [11:4]004hPLL2_1: 30-bit multiplier/divider value for frequency fVCO2_1
(for more information, see PLL Frequency Planning).
2Dh7:4PLL2_1N [3:0]
3:0PLL2_1R [8:5]000h
2Eh7:3PLL2_1R[4:0]
2:0PLL2_1Q [5:3]10h
2Fh7:5PLL2_1Q [2:0]
4:2PLL2_1P [2:0]010b
1:0VCO2_1_RANGE00bfVCO2_1 range selection:00 – fVCO2_1 < 125MHz
01 – 125MHz ≤ fVCO2_1 < 150MHz
10 – 150MHz ≤ fVCO2_1 < 175MHz
11 – fVCO2_1 ≥ 175MHz
(1) Writing data beyond 40h can adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used.
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
Table 9-6 PLL3 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
30h7:5SSC3_7 [2:0]000bSSC3: PLL3 SSC selection (modulation amount)(4)
4:2SSC3_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC3_5 [2:1]000b
31h7SSC3_5 [0]
6:4SSC3_4 [2:0]000b
3:1SSC3_3 [2:0]000b
0SSC3_2 [2]000b
32h7:6SSC3_2 [1:0]
5:3SSC3_1 [2:0]000b
2:0SSC3_0 [2:0]000b
33h7FS3_70bFS3_x: PLL3 frequency selection(4)
6FS3_60b0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
5FS3_50b
4FS3_40b
3FS3_30b
2FS3_20b
1FS3_10b
0FS3_00b
34h7MUX31bPLL3 multiplexer:0 – PLL3
1 – PLL3 bypass (PLL3 is in power down)
6M61bOutput Y6 multiplexer:0 – Pdiv4
1 – Pdiv6
5:4M710bOutput Y7 multiplexer:00 – Pdiv4-divider
01 – Pdiv6-divider
10 – Pdiv7-divider
11 – reserved
3:2Y6Y7_ST111bY6, Y7-State0/1definition:00 – Y6/Y7 disabled to 3-State and PLL3 power down
01 – Y6/Y7 disabled to 3-State
10 –Y6/Y7 disabled to low
11 – Y6/Y7 enabled
1:0Y6Y7_ST001b
35h7Y6Y7_70bY6Y7_x output state selection(4)
6Y6Y7_60b0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
5Y6Y7_50b
4Y6Y7_40b
3Y6Y7_30b
2Y6Y7_20b
1Y6Y7_11b
0Y6Y7_00b
36h7SSC3DC0bPLL3 SSC down/center selection:0 – Down  1 – Center
6:0Pdiv601h7-Bit Y6-output-divider Pdiv6:0 – Reset and stand-by   1-to-127 – Divider value
37h7—0bReserved – do not write others than 0
6:0Pdiv701h7-Bit Y7-output-divider Pdiv7:0 – Reset and stand-by   1-to-127 – Divider value
38h7:0PLL3_0N [11:4]004hPLL3_0: 30-bit multiplier/divider value for frequency fVCO3_0
(for more information, see PLL Frequency Planning).
39h7:4PLL3_0N [3:0]
3:0PLL3_0R [8:5]000h
3Ah7:3PLL3_0R[4:0]
2:0PLL3_0Q [5:3]10h
3Bh7:5PLL3_0Q [2:0]
4:2PLL3_0P [2:0]010b
1:0VCO3_0_RANGE00bfVCO3_0 range selection:00 – fVCO3_0 < 125MHz
01 – 125MHz ≤ fVCO3_0 < 150MHz
10 – 150MHz ≤ fVCO3_0 < 175MHz
11 – fVCO3_0 ≥ 175MHz
3Ch7:0PLL3_1N [11:4]004hPLL3_1: 30-bit multiplier/divider value for frequency fVCO3_1
(for more information, see PLL Frequency Planning).
3Dh7:4PLL3_1N [3:0]
3:0PLL3_1R [8:5]000h
3Eh7:3PLL3_1R[4:0]
2:0PLL3_1Q [5:3]10h
3Fh7:5PLL3_1Q [2:0]
4:2PLL3_1P [2:0]010b
1:0VCO3_1_RANGE00bfVCO3_1 range selection:00 – fVCO3_1 < 125MHz
01 – 125MHz ≤ fVCO3_1 < 150MHz
10 – 150MHz ≤ fVCO3_1 < 175MHz
11 – fVCO3_1 ≥ 175MHz
(1) Writing data beyond 40h can affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used.
(4) These are the bits of the Control Terminal register. The user can pre-define up to eight different control settings. At normal device operation, these setting can be selected by the external control pins, S0, S1, and S2.