SCAS892D February   2010  – July 2025 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Serial Interface
    5. 8.5 Programming
      1. 8.5.1 Data Protocol
      2. 8.5.2 Command Code Definition
      3. 8.5.3 Generic Programming Sequence
      4. 8.5.4 Byte Write Programming Sequence
      5. 8.5.5 Byte Read Programming Sequence
      6. 8.5.6 Block Write Programming Sequence
      7. 8.5.7 Block Read Programming Sequence
      8. 8.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 8.5.9 SDA and SCL Hardware Interface
  10. 9 Register Maps
    1. 9.1 SDA and SCL Configuration Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread-Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Frequency Planning
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.3.2 Default Device Setting

The internal EEPROM of CDCEx937-Q1 is preconfigured as shown in Figure 8-1. The input frequency is passed through to the output as a default. This allows the device to operate in default mode without the extra production step of programming the device. The default setting appears after power is supplied or after the power-down or power-up sequence, until the device is reprogrammed by the user to a different application configuration. A new register setting is programmed through the serial SDA and SCL interface.

CDCE937-Q1 CDCEL937-Q1 Default Device SettingFigure 8-1 Default Device Setting

Table 8-4 shows the factory default setting for the Control Terminal register (external control pins). In normal operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be selected with S0, as S1 and S2 are configured as programming pins in default mode.

Table 8-4 Factory Default Setting for Control Terminal Register(1)
Y1PLL1 SETTINGSPLL2 SETTINGSPLL3 SETTINGS
EXTERNAL CONTROL PINSOUTPUT SELECTFREQ. SELECTSSC SELECTOUTPUT SELECTFREQ. SELECTSSC SELECTOUTPUT SELECTFREQ. SELECTSSC SELECTOUTPUT SELECT
S2S1S0Y1FS1SSC1Y2Y3FS2SSC2Y4Y5FS3SSC3Y6Y7
SCL (I2C)SDA (I2C)03-statefVCO1_0off3-statefVCO2_0off3-statefVCO1_0off3-state
SCL (I2C)SDA (I2C)1EnabledfVCO1_0offEnabledfVCO2_0offEnabledfVCO1_0offEnabled
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interfaces, SDA and SCL. The pins do not have any control-pin function, but are internally interpreted as if S1 = 0 and S2 = 0. However, S0 is a control-pin, which in the default mode switches all outputs ON or OFF (as previously predefined).