SCAS892D February   2010  – July 2025 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Serial Interface
    5. 8.5 Programming
      1. 8.5.1 Data Protocol
      2. 8.5.2 Command Code Definition
      3. 8.5.3 Generic Programming Sequence
      4. 8.5.4 Byte Write Programming Sequence
      5. 8.5.5 Byte Read Programming Sequence
      6. 8.5.6 Block Write Programming Sequence
      7. 8.5.7 Block Read Programming Sequence
      8. 8.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 8.5.9 SDA and SCL Hardware Interface
  10. 9 Register Maps
    1. 9.1 SDA and SCL Configuration Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread-Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Frequency Planning
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.3.1 Control Terminal Setting

The CDCEx937-Q1 has three user-definable control terminals (S0, S1, and S2) that allow external control of device settings. The terminals can be programmed to any of the following settings:

  • Spread-spectrum clocking selection → spread type and spread amount selection
  • Frequency selection → switching between any of two user-defined frequencies
  • Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 8-1 and Table 8-2 explain these settings.

Table 8-1 Control Terminal Definition
EXTERNAL CONTROL BITSPLL1 SETTINGPLL2 SETTINGPLL3 SETTINGY1 SETTING
Control FunctionPLL Frequency SelectionSSC SelectionOutput Y2/Y3 SelectionPLL Frequency SelectionSSC SelectionOutput Y4/Y5 SelectionPLL Frequency SelectionSSC SelectionOutput Y6/Y7 SelectionOutput Y1 and Power-Down Selection
Table 8-2 PLLx Setting (Can Be Selected For Each PLL Individual)(1)
SSC SELECTION (CENTER/DOWN)
SSCx [3-BITS]CENTERDOWN
0000% (off)0% (off)
001±0.25%–0.25%
010±0.5%–0.5%
011±0.75%–0.75%
100±1.0%–1.0%
101±1.25%–1.25%
110±1.5%–1.5%
111±2.0%–2.0%
FREQUENCY SELECTION(2)
FSxFUNCTION
0Frequency0
1Frequency1
OUTPUT SELECTION(3) (Y2 ... Y7)
YxYxFUNCTION
0State0
1State1
(1) Center/Down-Spread, Frequency0/1, and State0/1 are user-definable in the PLLx Configuration register.
(2) Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
(3) State0/1 selection is valid for both outputs of the corresponding PLL module, and can be power down, 3-state, low, or active
Table 8-3 Y1 Setting(1)
Y1 SELECTION
Y1FUNCTION
0State 0
1State 1
(1) State0 and State1 are user-definable in the Generic Configuration register, and can be power down, 3-state, low, or active.

The S1/SDA and S2/SCL pins of the CDCEx937-Q1 are dual-function pins. In the default configuration, the pins are defined as SDA and SCL for the serial interface. The pins can be programmed as control-pins (S1/S2) by setting the relevant bits in the EEPROM. The changes to the Control register (Bit [6] of Byte [02]) have no effect until the changes are written into the EEPROM.

When the pins are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins (SDA and SCL).

S0 is not a multi-use pin, the pin is a control pin only.