SLAU966 February   2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of NXP M0 MCUs to MSPM0
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 MCUXpresso IDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 MCUXpresso Code Configuration Tool vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Memory Banks
        2. 3.2.2.2 Flash Memory Regions
        3. 3.2.2.3 NONMAIN Memory
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Power Modes
      3. 3.5.3 Entering Lower-Power Modes
    6. 3.6 Interrupt and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
      2. 3.6.2 Event Handler and Extended Interrupt and Event Controller (EXTI)
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6References

3.3 Power Up and Reset Summary and Comparison

Similar to NXP M0 devices, MSPM0 devices have a minimum operating voltage and have modules in place to make sure that the device starts up properly by holding the device or portions of the device in a reset state. Table 3-3 shows a comparison on how this is done between the two families and what modules control the power up process and reset across the families.

Table 3-3 Comparison of Power Up
Feature S32K1xx

KEA128x

 KM35x MSPM0 Devices
Modules governing power up and resets Reset Control Module Reset Control Module Reset Control Module Module governing power up and resets PMCU (Power Management and Clock Unit)
Voltage-Level Based Resets
POR (Power-On Reset) Complete device reset. First level voltage release for power up. Lowest voltage level for power down POR (Power-On Reset) Complete device reset. First level voltage release for power up. Lowest voltage level for power down.
BOR (Brownout Reset) with configurable levels Programmable Threshold for triggering resets Configurable BOR (Brownout Reset) Can be configured as a reset or interrupt, with different voltage thresholds.

NXP defines different reset types, while MSPM0 devices have different levels of reset states. For MSPM0 devices, the reset levels have a set order, and when a level is triggered, all subsequent levels are reset until the device is released into RUN mode. Table 3-4 gives a brief description of MSPM0 reset states. Figure 3-1 shows the relationship between all of the MSPM0 reset states.

Table 3-4 Comparison of Reset Domains
S32K1xx, KEA128x, KM35 Reset Domains MSPM0 Reset States (1)
Power reset domain Typical triggers are POR, BOR (3) POR existing content
No equivalent Boot reset (BOOTRST) (2) existing content
System reset domain Typical triggers are external pin reset, low voltage detect, WDT reset (3) System reset (SYSRST) existing content
No equivalent CPU-only reset (CPURST) existing content
RTC domain (3) existing content
(1) Not all reset triggers are described. Refer to the PMCU chapter of the device TRM for all available reset triggers.
(2) If BOOTRST cause was through NRST or software trigger, RTC, LFCLK, and LFXT/LFLCK_IN configurations and IOMUX settings are NOT reset to allow RTC to maintain operation through external reset.
(3) For specific reset triggers, see the Reset and Boot chapter of the NXP device-specific TRM.
MSPM0 Reset Levels Figure 3-1 MSPM0 Reset Levels