SLAU966 February   2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of NXP M0 MCUs to MSPM0
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 MCUXpresso IDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 MCUXpresso Code Configuration Tool vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Memory Banks
        2. 3.2.2.2 Flash Memory Regions
        3. 3.2.2.3 NONMAIN Memory
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Power Modes
      3. 3.5.3 Entering Lower-Power Modes
    6. 3.6 Interrupt and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
      2. 3.6.2 Event Handler and Extended Interrupt and Event Controller (EXTI)
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6References

5.3 Digital-to-Analog Converter (DAC)

The S32K1xx, KEA128x, and KM35x MCU families offers a basic DAC inside its COMP module. However, when migrating from the M0 family to the MSPM0 family, you can make use of the MSPM0 internal 12-bit DAC to generate analog voltages. The MSPM0 family offers a 12-bit DAC peripheral to perform digital-to-analog conversion for various applications. In the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual, the MSPM0 series data sheets, and the MSPM0 SDK, the 12-bit DAC peripheral is referred to as the DAC12. This differentiates the DAC12 from the 8-bit DACs that are available for use with each comparator peripheral included in a given MSPM0 device. Those additional 8-bit DACs are covered in the comparator section of this document. This DAC12 peripheral is only available on the MSPM0G family of devices.

The features of the 12-bit DAC peripherals for the MSPM0G are summarized in Table 5-4.

Table 5-4 DAC Feature Set Comparison
Feature S32K1xx KEA128x KM35x MSPM0G
Resolution 8-bit 6-bit 6-bit 12 bits (11 ENOB)
Output rate N/A N/A N/A 1 MSPS
Output channels 1 1 1 1 (1)
Data formats N/A N/A N/A 8-bit right aligned, 12-bit right aligned, two's complement or straight binary
DMA integration No No No Yes
Output routing Internal peripheral connection only: CMP Internal peripheral connection only: CMP DAC Output External Pins
Internal peripheral connection: CMP Internal peripheral connections: OPA IN+, COMP IN+, ADC0
Internal reference voltage Yes, 1V or VDDA Yes, 1.2V or VDDA Yes, 1.2V or VDDA Yes, 2.5V or 1.4V
External reference voltage No No No Yes
FIFO No No No Yes
Output buffer No No No Yes
Configurable output offset No No No Yes
Self-calibration mode No No No Yes
Automatic waveform generation No No No No
Sample and hold mode No No No No
Trigger sources Operation clock, trigger start signal N/A Trigger start signal Internal dedicated sample time generator, DMA interrupts/events, FIFO threshold interrupts/events, two hardware triggers (available from event fabric)
(1) Dual DAC channels are planned for future MSPM0G devices.

DAC12 code examples

Information about DAC12 code examples can be found in the MSPM0 SDK examples guide.