SLLSFR8B September 2025 – January 2026 TCAN5102-Q1
ADVANCE INFORMATION
The transmit FIFO is write only and is written to when a write command is issued to its address. Transmission will begin when the entire frame has been written into the buffer. All data bytes written after the end of the frame is ignored until a new transmit FIFO write is started. All writes to a transmit FIFO should be directed at the main address only, as each byte that is written is automatically shifted into the FIFO. For example, writing larger SPI messages than can be transferred in a single CAN message occurs over multiple CAN writes to the same address, since the SPI header bytes will tell the device how many data bytes to expect.
The size of each frame in the TX buffer is determined by the message length. There is a 2-byte header required at the beginning of each SPI FIFO element. The total length of the TX frame in the buffer is the sum of
| Byte | Bit | Field | Type | Reset | Description |
|---|---|---|---|---|---|
| 0 | 7 | STORE_RX | W | 0 | Whether to store the POCI
data for this message in the receive FIFO 0 = Do not store any data in the receive FIFO 1 = Save the received POCI data in the receive FIFO for this message |
| 6:3 | RSVD | R | 0 | Reserved | |
| 2:0 | CHAN | W | 0x0 | SPI Channel that was used for
this message Valid values 0-3 0 = SPI channel 0 1 = SPI channel 1 2 = SPI channel 2 3 = SPI channel 3 4 = SPI channel 4 5 = SPI channel 5 6 = SPI channel 6 7 = SPI channel 7 Note: A SPI channel
corresponds to a specific GPIO and requires that GPIO to be
assigned as a special function |
|
| 1 | 7:0 | NUM_BYTES | W | 0x0 | Number of bytes in the SPI
frame (does NOT include the above header bytes) Valid values 1-255. 0 is invalid. |