SLLSFR8B September   2025  – January 2026 TCAN5102-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Supply Characteristics
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 I2C Bus Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDD
      2. 7.3.2  PROG Pin
      3. 7.3.3  DIGFLTR Pin
      4. 7.3.4  GPIOx and Pin Muxing Special Functions
        1. 7.3.4.1 GPIO Synchronization
      5. 7.3.5  EEPROM
      6. 7.3.6  SPI Controller
      7. 7.3.7  UART Controller
      8. 7.3.8  I2C Controller
        1. 7.3.8.1 I2C Stuck Bus Recovery
      9. 7.3.9  PWM Controller
      10. 7.3.10 CAN Transceiver Control Pins
      11. 7.3.11 Under-Voltage Lockout and Unpowered Device
    4. 7.4 Device Functional Modes
      1. 7.4.1 Init Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Normal Mode
    5. 7.5 Programming
      1. 7.5.1 Device Programming via SPI Peripheral Mode
      2. 7.5.2 CAN FD Light Protocol
        1. 7.5.2.1 CAN Frame Format
      3. 7.5.3 Message RAM (MRAM) and IP Enable
      4. 7.5.4 SPI Controller
        1. 7.5.4.1 SPI Pins
          1. 7.5.4.1.1 SPI Clock (SCLK)
          2. 7.5.4.1.2 Peripheral In Controller Out (PICO)
          3. 7.5.4.1.3 Peripheral Out Controller In (POCI)
          4. 7.5.4.1.4 Chip Select (CS or nCS)
        2. 7.5.4.2 SPI Clock Generator
        3. 7.5.4.3 SPI Control Protocol
          1. 7.5.4.3.1 SPI Write Example 1
          2. 7.5.4.3.2 SPI Read Example 1
      5. 7.5.5 UART Controller
        1. 7.5.5.1 UART Baud Rate Generation and Fractional Divisor
        2. 7.5.5.2 UART Control Protocol
          1. 7.5.5.2.1 UART Write Example 1
          2. 7.5.5.2.2 UART Read Example 1
      6. 7.5.6 I2C Controller
        1. 7.5.6.1 I2C Baud Rate Generation
        2. 7.5.6.2 I2C Stuck Bus Recovery
        3. 7.5.6.3 I2C Control Protocol
          1. 7.5.6.3.1 I2C Write Example 1
          2. 7.5.6.3.2 I2C Read Example 1
      7. 7.5.7 PWM and Trapezoidal PWM Ramp Profiles
        1. 7.5.7.1 Trapezoidal Ramp Control
          1. 7.5.7.1.1 Duty Cycle Ramping
          2. 7.5.7.1.2 Switching Frequency Ramping
          3. 7.5.7.1.3 Off-Ramp
        2. 7.5.7.2 PWM Clock Generator
        3. 7.5.7.3 PWM Duty Cycle
        4. 7.5.7.4 Ramp Slope and Scale Factor
          1. 7.5.7.4.1 Duty Cycle Ramp Slope
          2. 7.5.7.4.2 Switching Frequency Ramp Slope
        5. 7.5.7.5 Automatic Deceleration and Stop Conditions
          1. 7.5.7.5.1 Automatic Deceleration Off-Ramp with Pulse Counting
          2. 7.5.7.5.2 Automatic Deceleration/Off-Ramp with GPIO Input
        6. 7.5.7.6 Duty Cycle Ramp Example
        7. 7.5.7.7 Frequency Ramp Example
        8. 7.5.7.8 Static On Example
    6. 7.6 Register Maps
      1. 7.6.1 DEVICE Registers
        1. 7.6.1.1  DEV_ID[y] Register (Offset = 0h + formula) [Reset = 0032303135414354h]
        2. 7.6.1.2  DEV_ID_REV Register (Offset = 8h) [Reset = 10h]
        3. 7.6.1.3  DEV_CMD Register (Offset = 9h) [Reset = 00h]
        4. 7.6.1.4  DEV_CFG_EN Register (Offset = Ah) [Reset = 00h]
        5. 7.6.1.5  DEV_CFG_BR Register (Offset = Bh) [Reset = 10h]
        6. 7.6.1.6  DEV_CFG_ID_0 Register (Offset = Ch) [Reset = 00h]
        7. 7.6.1.7  DEV_CFG_ID_1 Register (Offset = Dh) [Reset = 00h]
        8. 7.6.1.8  DEV_CFG_ID_BCST_0 Register (Offset = Eh) [Reset = 00h]
        9. 7.6.1.9  DEV_CFG_ID_BCST_1 Register (Offset = Fh) [Reset = 00h]
        10. 7.6.1.10 DEV_CFG_ID_BCST_MASK_0 Register (Offset = 10h) [Reset = 00h]
        11. 7.6.1.11 DEV_CFG_ID_BCST_MASK_1 Register (Offset = 11h) [Reset = 00h]
        12. 7.6.1.12 DEV_CFG_NVM_PROG_CODE Register (Offset = 12h) [Reset = 00h]
        13. 7.6.1.13 DEV_CFG_NVM_PROG Register (Offset = 13h) [Reset = 00h]
        14. 7.6.1.14 INT_CFG Register (Offset = 1Dh) [Reset = 00h]
        15. 7.6.1.15 DEV_IE_0 Register (Offset = 1Eh) [Reset = 00h]
        16. 7.6.1.16 DEV_IE_1 Register (Offset = 1Fh) [Reset = 00h]
        17. 7.6.1.17 MRAM_IP_CFG Register (Offset = 20h) [Reset = 00h]
        18. 7.6.1.18 IO_CFG_0 Register (Offset = 21h) [Reset = 00h]
        19. 7.6.1.19 IO_CFG_1 Register (Offset = 22h) [Reset = 00h]
        20. 7.6.1.20 IO_OE_0 Register (Offset = 23h) [Reset = 00h]
        21. 7.6.1.21 IO_OE_1 Register (Offset = 24h) [Reset = 00h]
        22. 7.6.1.22 IO_OD_0 Register (Offset = 25h) [Reset = 00h]
        23. 7.6.1.23 IO_OD_1 Register (Offset = 26h) [Reset = 00h]
        24. 7.6.1.24 IO_RE_0 Register (Offset = 27h) [Reset = 00h]
        25. 7.6.1.25 IO_RE_1 Register (Offset = 28h) [Reset = 00h]
        26. 7.6.1.26 IO_PU_0 Register (Offset = 29h) [Reset = 00h]
        27. 7.6.1.27 IO_PU_1 Register (Offset = 2Ah) [Reset = 00h]
        28. 7.6.1.28 IO_POL_0 Register (Offset = 2Bh) [Reset = 00h]
        29. 7.6.1.29 IO_POL_1 Register (Offset = 2Ch) [Reset = 00h]
        30. 7.6.1.30 IO_OUTPUT_0 Register (Offset = 2Dh) [Reset = 00h]
        31. 7.6.1.31 IO_OUTPUT_1 Register (Offset = 2Eh) [Reset = 00h]
        32. 7.6.1.32 IO_INPUT_0 Register (Offset = 2Fh) [Reset = 00h]
        33. 7.6.1.33 IO_INPUT_1 Register (Offset = 30h) [Reset = 00h]
        34. 7.6.1.34 IR_STATUS Register (Offset = 31h) [Reset = 00h]
        35. 7.6.1.35 DEV_IR Register (Offset = 32h) [Reset = 00h]
        36. 7.6.1.36 SPI_IR Register (Offset = 33h) [Reset = 00h]
        37. 7.6.1.37 UART_IR Register (Offset = 34h) [Reset = 00h]
        38. 7.6.1.38 I2C_IR Register (Offset = 35h) [Reset = 00h]
        39. 7.6.1.39 PWM0_IR Register (Offset = 36h) [Reset = 00h]
        40. 7.6.1.40 PWM1_IR Register (Offset = 37h) [Reset = 00h]
      2. 7.6.2 SPI Registers
        1. 7.6.2.1  SPI_CREL Register (Offset = 1000h) [Reset = 87h]
        2. 7.6.2.2  SPI_SCRATCH Register (Offset = 1001h) [Reset = 00h]
        3. 7.6.2.3  SPI_CTRL Register (Offset = 1002h) [Reset = 00h]
        4. 7.6.2.4  SPI_CFG_0 Register (Offset = 1003h) [Reset = 00h]
        5. 7.6.2.5  SPI_CFG_1 Register (Offset = 1004h) [Reset = 00h]
        6. 7.6.2.6  SPI_DR_0 Register (Offset = 1005h) [Reset = 00h]
        7. 7.6.2.7  SPI_DR_1 Register (Offset = 1006h) [Reset = 00h]
        8. 7.6.2.8  SPI_DR_2 Register (Offset = 1007h) [Reset = 00h]
        9. 7.6.2.9  SPI_DR_3 Register (Offset = 1008h) [Reset = 00h]
        10. 7.6.2.10 SPI_CHAN_EN Register (Offset = 1009h) [Reset = 00h]
        11. 7.6.2.11 SPI_CS_POL Register (Offset = 100Ah) [Reset = 00h]
        12. 7.6.2.12 SPI_FIFO_CTRL Register (Offset = 100Bh) [Reset = 0h]
        13. 7.6.2.13 SPI_IE_0 Register (Offset = 100Ch) [Reset = 00h]
        14. 7.6.2.14 SPI_IE_1 Register (Offset = 100Dh) [Reset = 00h]
        15. 7.6.2.15 SPI_IR Register (Offset = 100Eh) [Reset = 00h]
        16. 7.6.2.16 SPI_FS Register (Offset = 100Fh) [Reset = 80h]
        17. 7.6.2.17 SPI_TX_FIFO Register (Offset = 1010h) [Reset = 0000h]
        18. 7.6.2.18 SPI_RX_FIFO Register (Offset = 1010h) [Reset = 0000h]
        19. 7.6.2.19 SPI_RXFS Register (Offset = 1011h) [Reset = 00h]
        20. 7.6.2.20 SPI_TXFS Register (Offset = 1012h) [Reset = 00h]
        21. 7.6.2.21 SPI_TXES Register (Offset = 1013h) [Reset = 00h]
      3. 7.6.3 SPI Data FIFOs
        1. 7.6.3.1 SPI Transmit FIFO (address = h1010)
        2. 7.6.3.2 SPI Receive FIFO (address = h1010)
      4. 7.6.4 UART Registers
        1. 7.6.4.1  UART_CREL Register (Offset = 2000h) [Reset = 10h]
        2. 7.6.4.2  UART_SCRATCH Register (Offset = 2001h) [Reset = 00h]
        3. 7.6.4.3  UART_CTRL Register (Offset = 2002h) [Reset = 04h]
        4. 7.6.4.4  UART_BR_LSB Register (Offset = 2003h) [Reset = 00h]
        5. 7.6.4.5  UART_BR_MSB Register (Offset = 2004h) [Reset = 00h]
        6. 7.6.4.6  UART_BR_FRAC Register (Offset = 2005h) [Reset = 00h]
        7. 7.6.4.7  UART_FIFO_CTRL Register (Offset = 2006h) [Reset = 01h]
        8. 7.6.4.8  UART_IE_0 Register (Offset = 2007h) [Reset = 00h]
        9. 7.6.4.9  UART_IE_1 Register (Offset = 2008h) [Reset = 00h]
        10. 7.6.4.10 UART_IR Register (Offset = 2009h) [Reset = 00h]
        11. 7.6.4.11 UART_STATUS Register (Offset = 200Ah) [Reset = 60h]
        12. 7.6.4.12 UART_RXFS Register (Offset = 200Bh) [Reset = 00h]
        13. 7.6.4.13 UART_TXFS Register (Offset = 200Ch) [Reset = 00h]
        14. 7.6.4.14 UART_RX_FIFO Register (Offset = 2010h) [Reset = 00h]
        15. 7.6.4.15 UART_TX_FIFO Register (Offset = 2010h) [Reset = 00h]
        16. 7.6.4.16 UART_RX_ERR_STATUS Register (Offset = 2011h) [Reset = 00h]
      5. 7.6.5 UART Data FIFOs
        1. 7.6.5.1 UART Transmit FIFO (address = h2010)
        2. 7.6.5.2 UART Receive FIFO (address = h2010)
        3. 7.6.5.3 UART Receive Error Status (address = h2011)
      6. 7.6.6 I2C Registers
        1. 7.6.6.1  I2C_CREL Register (Offset = 3000h) [Reset = 10h]
        2. 7.6.6.2  I2C_SCRATCH Register (Offset = 3001h) [Reset = 00h]
        3. 7.6.6.3  I2C_CTRL Register (Offset = 3002h) [Reset = 18h]
        4. 7.6.6.4  I2C_BR Register (Offset = 3003h) [Reset = 18h]
        5. 7.6.6.5  I2C_FIFO_CTRL Register (Offset = 3004h) [Reset = 00h]
        6. 7.6.6.6  I2C_IE_0 Register (Offset = 3005h) [Reset = 00h]
        7. 7.6.6.7  I2C_IE_1 Register (Offset = 3006h) [Reset = 00h]
        8. 7.6.6.8  I2C_IR Register (Offset = 3007h) [Reset = 00h]
        9. 7.6.6.9  I2C_STATUS Register (Offset = 3008h) [Reset = XXh]
        10. 7.6.6.10 I2C_FS Register (Offset = 3009h) [Reset = 00h]
        11. 7.6.6.11 I2C_RXFS Register (Offset = 300Ah) [Reset = 00h]
        12. 7.6.6.12 I2C_TXFS Register (Offset = 300Bh) [Reset = 00h]
        13. 7.6.6.13 I2C_TXES Register (Offset = 300Ch) [Reset = 00h]
      7. 7.6.7 I2C Data FIFOs
        1. 7.6.7.1 I2C Transmit FIFO (address = h3010)
        2. 7.6.7.2 I2C Receive FIFO (address = h3010)
      8. 7.6.8 PWM0 Registers
        1. 7.6.8.1  PWM1_ACTION Register (Offset = 4000h) [Reset = 00h]
        2. 7.6.8.2  PWM0_CTRL Register (Offset = 4000h) [Reset = 11h]
        3. 7.6.8.3  PWM0_IE0 Register (Offset = 4001h) [Reset = 00h]
        4. 7.6.8.4  PWM0_IE1 Register (Offset = 4002h) [Reset = 00h]
        5. 7.6.8.5  PWM0_IR Register (Offset = 4003h) [Reset = 00h]
        6. 7.6.8.6  PWM0_STATUS Register (Offset = 4004h) [Reset = 00h]
        7. 7.6.8.7  PWM0_CUR_PULSE[y] Register (Offset = 4005h + formula) [Reset = 00000000h]
        8. 7.6.8.8  PWM0_CUR_VAL_MSB Register (Offset = 4009h) [Reset = 00h]
        9. 7.6.8.9  PWM0_CUR_VAL_LSB Register (Offset = 400Ah) [Reset = 00h]
        10. 7.6.8.10 PWM0_CONST_MSB Register (Offset = 400Bh) [Reset = 00h]
        11. 7.6.8.11 PWM0_CONST_LSB Register (Offset = 400Ch) [Reset = 00h]
        12. 7.6.8.12 PWM0_STOP_VAL_FRAC_F Register (Offset = 400Dh) [Reset = 00h]
        13. 7.6.8.13 PWM0_STOP_VAL_MSB Register (Offset = 400Eh) [Reset = 00h]
        14. 7.6.8.14 PWM0_STOP_VAL_LSB Register (Offset = 400Fh) [Reset = 00h]
        15. 7.6.8.15 PWM0_STOP_SL_MSB Register (Offset = 4010h) [Reset = 00h]
        16. 7.6.8.16 PWM0_STOP_SL_MID Register (Offset = 4011h) [Reset = 00h]
        17. 7.6.8.17 PWM0_STOP_SL_LSB Register (Offset = 4012h) [Reset = 00h]
        18. 7.6.8.18 PWM0_START_VAL_FRAC_F Register (Offset = 4013h) [Reset = 00h]
        19. 7.6.8.19 PWM0_START_VAL_MSB Register (Offset = 4014h) [Reset = 00h]
        20. 7.6.8.20 PWM0_START_VAL_LSB Register (Offset = 4015h) [Reset = 00h]
        21. 7.6.8.21 PWM0_START_SL_MSB Register (Offset = 4016h) [Reset = 00h]
        22. 7.6.8.22 PWM0_START_SL_MID Register (Offset = 4017h) [Reset = 00h]
        23. 7.6.8.23 PWM0_START_SL_LSB Register (Offset = 4018h) [Reset = 00h]
        24. 7.6.8.24 PWM0_END_VAL_CONST_FRAC_F Register (Offset = 4019h) [Reset = 00h]
        25. 7.6.8.25 PWM0_END_VAL_MSB Register (Offset = 401Ah) [Reset = 00h]
        26. 7.6.8.26 PWM0_END_VAL_LSB Register (Offset = 401Bh) [Reset = 00h]
        27. 7.6.8.27 PWM0_PULSE_STOP_RAMP[y] Register (Offset = 401Ch + formula) [Reset = 00000000h]
        28. 7.6.8.28 PWM0_PULSE_MAX[y] Register (Offset = 4020h + formula) [Reset = 00000000h]
        29. 7.6.8.29 PWM0_ACTION Register (Offset = 4024h) [Reset = 00h]
        30. 7.6.8.30 PWM0_IAS_CTRL Register (Offset = 4030h) [Reset = 00h]
      9. 7.6.9 PWM1 Registers
        1. 7.6.9.1  PWM1_CTRL Register (Offset = 4100h) [Reset = 11h]
        2. 7.6.9.2  PWM1_IE0 Register (Offset = 4101h) [Reset = 00h]
        3. 7.6.9.3  PWM1_IE1 Register (Offset = 4102h) [Reset = 00h]
        4. 7.6.9.4  PWM1_IR Register (Offset = 4103h) [Reset = 00h]
        5. 7.6.9.5  PWM1_STATUS Register (Offset = 4104h) [Reset = 00h]
        6. 7.6.9.6  PWM1_CUR_PULSE[y] Register (Offset = 4105h + formula) [Reset = 00000000h]
        7. 7.6.9.7  PWM1_CUR_VAL_MSB Register (Offset = 4109h) [Reset = 00h]
        8. 7.6.9.8  PWM1_CUR_VAL_LSB Register (Offset = 410Ah) [Reset = 00h]
        9. 7.6.9.9  PWM1_CONST_MSB Register (Offset = 410Bh) [Reset = 00h]
        10. 7.6.9.10 PWM1_CONST_LSB Register (Offset = 410Ch) [Reset = 00h]
        11. 7.6.9.11 PWM1_STOP_VAL_FRAC_F Register (Offset = 410Dh) [Reset = 00h]
        12. 7.6.9.12 PWM1_STOP_VAL_MSB Register (Offset = 410Eh) [Reset = 00h]
        13. 7.6.9.13 PWM1_STOP_VAL_LSB Register (Offset = 410Fh) [Reset = 00h]
        14. 7.6.9.14 PWM1_STOP_SL_MSB Register (Offset = 4110h) [Reset = 00h]
        15. 7.6.9.15 PWM1_STOP_SL_MID Register (Offset = 4111h) [Reset = 00h]
        16. 7.6.9.16 PWM1_STOP_SL_LSB Register (Offset = 4112h) [Reset = 00h]
        17. 7.6.9.17 PWM1_START_VAL_FRAC_F Register (Offset = 4113h) [Reset = 00h]
        18. 7.6.9.18 PWM1_START_VAL_MSB Register (Offset = 4114h) [Reset = 00h]
        19. 7.6.9.19 PWM1_START_VAL_LSB Register (Offset = 4115h) [Reset = 00h]
        20. 7.6.9.20 PWM1_START_SL_MSB Register (Offset = 4116h) [Reset = 00h]
        21. 7.6.9.21 PWM1_START_SL_MID Register (Offset = 4117h) [Reset = 00h]
        22. 7.6.9.22 PWM1_START_SL_LSB Register (Offset = 4118h) [Reset = 00h]
        23. 7.6.9.23 PWM1_END_VAL_CONST_FRAC_F Register (Offset = 4119h) [Reset = 00h]
        24. 7.6.9.24 PWM1_END_VAL_MSB Register (Offset = 411Ah) [Reset = 00h]
        25. 7.6.9.25 PWM1_END_VAL_LSB Register (Offset = 411Bh) [Reset = 00h]
        26. 7.6.9.26 PWM1_PULSE_STOP_RAMP[y] Register (Offset = 411Ch + formula) [Reset = 00000000h]
        27. 7.6.9.27 PWM1_PULSE_MAX[y] Register (Offset = 4120h + formula) [Reset = 00000000h]
        28. 7.6.9.28 PWM1_ACTION Register (Offset = 4124h) [Reset = 00h]
        29. 7.6.9.29 PWM1_IAS_CTRL Register (Offset = 4130h) [Reset = 00h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

7.6.5.2 UART Receive FIFO (address = h2010)

The receive FIFO is read only and reads out the next byte of data in the RX FIFO. It's recommended reading the UART_RXFS register to see how many bytes are in the FIFO before performing a burst read. A burst read to this register returns multiple bytes of data up to the number of requested bytes.

At the end of the data bytes, a global status byte is appended, which is the logical bitwise OR of all bytes statuses. This is used to signal if any of the bytes that were read have any non-normal statuses. If the status byte returns a non-normal status, a read to the UART_RX_ERR_STATUS register gives a status byte for each corresponding data byte that was read most recently, allowing the user to determine which byte had a non-normal status.

A normal global status byte returns 0x01. A 0x00 denotes that invalid/read overrun has occurred.

A read from an empty RX buffer will return 0 and a status byte of 0. Frames are always read in the order that received.

The RX buffer can be cleared (all frames discarded) by a write of 1 to the UART Clear RX FIFO bit (UART_FIFO_CTRL[1]).

See UART Control Protocol for more information and examples.

Note: If the receive FIFO is full, all new incoming messages is discarded and an interrupt set to alert the processor that a message was lost.

TCAN5102-Q1 UART Receive FIFO Burst ReadFigure 7-98 UART Receive FIFO Burst Read
Table 7-140 UART Receive FIFO Descriptions (with Global Status Byte)
ByteBitFieldTypeResetDescription
0 to N-17:0DATAR0Byte of data received
N (Last)7:5RSVDR0x0Reserved
4BRKR0Set when a break condition was detected. The data byte is returned as 0x00 for a break
0 = No break detected in bytes
1 = At least one byte is a break
3FRAMER0When set, a byte was received with a framing error (invalid stop bit count)
0 = No framing error detected in bytes
1 = At least one byte had a framing error
2PARR0Parity Error. When set, at least 1 byte was received with an invalid parity bit.
0 = All parity bits were valid
1 = At least one parity bit was incorrect
1NO_RXR0Empty Byte/No RX. When set, at least 1 byte was an invalid byte and a read overrun has occurred.
0 = All bytes are valid
1 = At least one byte is invalid
0NO_ERRR0No Error. When set, all bytes were received successfully.
0 = At least one byte has a non-normal status
1 = All bytes were received successfully.