SLLSFZ8 Data sheet

SLLSFZ8 November 2025 MCF8329HS-Q1

PRODUCTION DATA

8.2 Fault_Configuration Registers

Table 8-17 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in Table 8-17 should be considered as reserved locations and the register contents should not be modified.

Table 8-17 FAULT_CONFIGURATION Registers

Offset	Acronym	Register Name	Section
90h	FAULT_CONFIG1	Fault Configuration1	Section 8.2.1
92h	FAULT_CONFIG2	Fault Configuration2	Section 8.2.2

Complex bit access types are encoded to fit into small table cells. Table 8-18 shows the codes that are used for access types in this section.

Table 8-18 Fault_Configuration Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.2.1 FAULT_CONFIG1 Register (Offset = 90h) [Reset = 00000000h]

FAULT_CONFIG1 is shown in Figure 8-15 and described in Table 8-19.

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Figure 8-15 FAULT_CONFIG1 Register

31	30	29	28	27	26	25	24
PARITY	ILIMIT				HW_LOCK_ILIMIT
R-0h	R/W-0h				R/W-0h

23	22	21	20	19	18	17	16
HW_LOCK_ILIMIT	LOCK_ILIMIT				EEP_FAULT_MODE	LOCK_ILIMIT_MODE
R/W-0h	R/W-0h				R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
LOCK_ILIMIT_MODE	LOCK_ILIMIT_DEG				LCK_RETRY
R/W-0h	R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
LCK_RETRY	I2C_CRC_ERR_MODE	MTR_LCK_MODE			MIN_VM_MODE	MAX_VM_MODE	SATURATION_FLAGS_EN
R/W-0h	R/W-0h	R/W-0h			R/W-0h	R/W-0h	R/W-0h

Table 8-19 FAULT_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30-27	ILIMIT	R/W	0h	Phase current peak limit (% of BASE_CURRENT) 0h = 5% 1h = 10% 2h = 15% 3h = 20% 4h = 25% 5h = 30% 6h = 40% 7h = 45% 8h = 50% 9h = 55% Ah = 60% Bh = 65% Ch = 70% Dh = 75% Eh = 80% Fh = 85%
26-23	HW_LOCK_ILIMIT	R/W	0h	Comparator based lock detection current limit (% of BASE_CURRENT) 0h = 0% 1h = 6.7% 2h = 13.3% 3h = 20% 4h = 26.7% 5h = 33.3% 6h = 40% 7h = 46.7% 8h = 53.3% 9h = 60% Ah = 66.7% Bh = 73.3% Ch = 80% Dh = 86.7% Eh = 93.3% Fh = 100%
22-19	LOCK_ILIMIT	R/W	0h	ADC based lock detection current limit (% of BASE_CURRENT) 0h = 10% 1h = 15% 2h = 20% 3h = 25% 4h = 30% 5h = 40% 6h = 50% 7h = 55% 8h = 60% 9h = 65% Ah = 70% Bh = 75% Ch = 80% Dh = 85% Eh = 90% Fh = 95%
18	EEP_FAULT_MODE	R/W	0h	EEPROM error fault mode 0h = EEPROM fault causes latched fault; nFAULT is active; Gate driver is tristated 1h = EEPROM fault causes report only but no action is taken; nFAULT is active
17-15	LOCK_ILIMIT_MODE	R/W	0h	Lock detection current limit fault mode 0h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 2h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 3h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active 4h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 6h = Ilimit lock detection current limit is in report only but no action is taken; nFAULT active 7h = ILIMIT LOCK is disabled
14-11	LOCK_ILIMIT_DEG	R/W	0h	Lock detection current limit fault deglitch time 0h = No deglitch 1h = 0.1 ms 2h = 0.2 ms 3h = 0.5 ms 4h = 1 ms 5h = 2.5 ms 6h = 5 ms 7h = 7.5 ms 8h = 10 ms 9h = 25 ms Ah = 50 ms Bh = 75 ms Ch = 100 ms Dh = 200 ms Eh = 500 ms Fh = 1000 ms
10-7	LCK_RETRY	R/W	0h	Lock detection fault retry time 0h = 300 ms 1h = 500 ms 2h = 1 s 3h = 2 s 4h = 3 s 5h = 4 s 6h = 5 s 7h = 6 s 8h = 7 s 9h = 8 s Ah = 9 s Bh = 10 s Ch = 11 s Dh = 12 s Eh = 13 s Fh = 14 s
6	I2C_CRC_ERR_MODE	R/W	0h	I2C CRC error fault mode 0h = CRC error on I2C causes latched fault; nFAULT is active; Gate driver is tristated 1h = CRC error on I2C causes report only but no action is taken; nFAULT is active
5-3	MTR_LCK_MODE	R/W	0h	Motor lock fault mode 0h = Motor lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 2h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 3h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active 4h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode(All low side FETs are turned ON); nFAULT active 6h = Motor lock detection current limit is in report only but no action is taken; nFAULT active 7h = MTR LOCK is disabled
2	MIN_VM_MODE	R/W	0h	PVDD undervoltage fault recovery mode 0h = PVDD under voltage fault causes latched fault; nFAULT is active; Gate driver is tristated 1h = PVDD under voltage fault clears automatically if the PVDD voltage is more than (MIN_VM_MOTOR + VOLTAGE_HYSTERESIS);Gate driver is tristated; nFAULT active
1	MAX_VM_MODE	R/W	0h	PVDD overvoltage fault recovery mode 0h = PVDD over voltage fault causes latched fault; nFAULT is active; Gate driver is tristated 1h = PVDD over voltage fault clears automatically if the PVDD voltage is less than (MAX_VM_MOTOR - VOLTAGE_HYSTERESIS);Gate driver is tristated; nFAULT active
0	SATURATION_FLAGS_EN	R/W	0h	Current and speed loop saturation indication enable 0h = Disable 1h = Enable

8.2.2 FAULT_CONFIG2 Register (Offset = 92h) [Reset = 00000000h]

FAULT_CONFIG2 is shown in Figure 8-16 and described in Table 8-20.

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Figure 8-16 FAULT_CONFIG2 Register

31	30	29	28	27	26	25	24
PARITY	LOCK1_EN	LOCK2_EN	LOCK3_EN	LOCK_ABN_SPEED			ABNORMAL_BEMF_THR
R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
ABNORMAL_BEMF_THR		NO_MTR_THR			HW_LOCK_ILIMIT_MODE
R/W-0h		R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
HW_LOCK_ILIMIT_DEG			VOLTAGE_HYSTERESIS		MIN_VM_MOTOR
R/W-0h			R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
MIN_VM_MOTOR	MAX_VM_MOTOR				AUTO_RETRY_TIMES
R/W-0h	R/W-0h				R/W-0h

Table 8-20 FAULT_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30	LOCK1_EN	R/W	0h	Lock 1 (abnormal speed fault) enable 0h = Disable 1h = Enable
29	LOCK2_EN	R/W	0h	Lock 2 (abnormal BEMF fault) enable 0h = Disable 1h = Enable
28	LOCK3_EN	R/W	0h	Lock 3 (no motor fault) enable 0h = Disable 1h = Enable
27-25	LOCK_ABN_SPEED	R/W	0h	Abnormal speed lock detection threshold (% of MAX_SPEED) 0h = 130% 1h = 140% 2h = 150% 3h = 160% 4h = 170% 5h = 180% 6h = 190% 7h = 200%
24-22	ABNORMAL_BEMF_THR	R/W	0h	Abnormal BEMF lock detection threshold (% of expected Back-EMF) Expected Back-EMF = MOTOR_BEMF_CONST × Estimated speed in Hz 0h = 40% 1h = 45% 2h = 50% 3h = 55% 4h = 60% 5h = 65% 6h = 67.5% 7h = 70%
21-19	NO_MTR_THR	R/W	0h	No motor fault condition is true if the motor phase current is less than NO_MTR_THR (% of BASE_CURRENT) 0h = 1% 1h = 2% 2h = 3% 3h = 4% 4h = 5% 5h = 7.5% 6h = 10% 7h = 20%
18-16	HW_LOCK_ILIMIT_MODE	R/W	0h	Hardware lock detection fault mode 0h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 2h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 3h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active 4h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 6h = Hardware Ilimit lock detection current limit is in report only but no action is taken; nFAULT active 7h = HARDWARE ILIMIT LOCK is disabled
15-13	HW_LOCK_ILIMIT_DEG	R/W	0h	Hardware lock detection current limit deglitch time 0h = Not Applicable 1h = Not Applicable 2h = 2 µs 3h = 3 µs 4h = 4 µs 5h = 5 µs 6h = 6 µs 7h = 7 µs
12-11	VOLTAGE_HYSTERESIS	R/W	0h	Hysteresis for PVDD overvoltage and undervoltage faults. Fault triggered at threshold, cleared at threshold ± hysteresis (+ for UV, - for OV) 0h = 1 V 1h = 1.5 V 2h = 2 V 3h = 3 V
10-7	MIN_VM_MOTOR	R/W	0h	PVDD undervoltage fault threshold (minimum DC bus voltage for running motor) 0h = No Limit 1h = 6 V 2h = 7 V 3h = 8 V 4h = 9 V 5h = 12 V 6h = 14 V 7h = 16 V 8h = 18 V 9h = 20 V Ah = 24 V Bh = 26 V Ch = 28 V Dh = 30 V Eh = 32 V Fh = 36 V
6-3	MAX_VM_MOTOR	R/W	0h	PVDD overvoltage fault threshold (maximum DC bus voltage for running motor) 0h = No Limit 1h = 16 V 2h = 18 V 3h = 20 V 4h = 22 V 5h = 26 V 6h = 28 V 7h = 32 V 8h = 34 V 9h = 36 V Ah = 38 V Bh = 40 V Ch = 44 V Dh = 48 V Eh = 54 V Fh = 58 V
2-0	AUTO_RETRY_TIMES	R/W	0h	Automatic fault retry attempts. This is used only if any of the fault mode is configured as "retry" 0h = No Limit 1h = 2 2h = 3 3h = 5 4h = 7 5h = 10 6h = 15 7h = 20