SLLSFZ8 November   2025 MCF8329HS-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  Low-Side Current Sense Amplifier
      5. 7.3.5  Device Interface Modes
        1. 7.3.5.1 Interface - Control and Monitoring
        2. 7.3.5.2 I2C Interface
      6. 7.3.6  Motor Control Input Options
        1. 7.3.6.1 Analog-Mode Motor Control
        2. 7.3.6.2 PWM-Mode Motor Control
        3. 7.3.6.3 Frequency-Mode Motor Control
        4. 7.3.6.4 I2C based Motor Control
        5. 7.3.6.5 Input Control Signal Profiles
          1. 7.3.6.5.1 Linear Control Profiles
          2. 7.3.6.5.2 Staircase Control Profiles
          3. 7.3.6.5.3 Forward-Reverse Profiles
          4. 7.3.6.5.4 Multi-Reference Mode Operation
          5. 7.3.6.5.5 Input Reference Transfer Function without Profiler
      7. 7.3.7  Bootstrap Capacitor Initial Charging
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
          1. 7.3.9.3.1 Reverse Drive Tuning
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open Loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 Closed loop accelerate
        2. 7.3.10.2 Speed PI Control
        3. 7.3.10.3 Current PI Control
        4. 7.3.10.4 Overmodulation
        5. 7.3.10.5 Power Loop
        6. 7.3.10.6 Modulation Index Control
        7. 7.3.10.7 Motor Speed Limit
        8. 7.3.10.8 Input DC Power Limit
      11. 7.3.11 Maximum Torque Per Ampere (MTPA) Control
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Single Hall Sensor Operation
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Active Braking
      18. 7.3.18 Output PWM Switching Frequency
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behavior During Fault
      23. 7.3.23 Protections
        1. 7.3.23.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.23.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.23.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.23.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.23.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.23.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.23.7  Thermal Shutdown (OTSD)
        8. 7.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE = 111b)
        9. 7.3.23.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.23.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 111b)
        10. 7.3.23.10 Motor Lock (MTR_LCK)
          1. 7.3.23.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xb or 010b)
          2. 7.3.23.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE = 011b or 10xb)
          3. 7.3.23.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 110b)
          4. 7.3.23.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 111b)
        11. 7.3.23.11 Motor Lock Detection
          1. 7.3.23.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.23.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.23.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.23.12 MPET Faults
        13. 7.3.23.13 IPD Faults
        14. 7.3.23.14 Dry Run Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 Oscillator Source
      3. 7.5.3 External Watchdog with MCU Reset
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Algorithm_Control Registers
    4. 9.4 Device_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Typical Applications
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3.      Gate Drive Current
      4.      Gate Resistor Selection
      5.      System Considerations in High Power Designs
      6.      Capacitor Voltage Ratings
      7.      External Power Stage Components
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Bulk Capacitance
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Thermal Considerations
        1. 10.4.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

8.1 Algorithm_Configuration Registers

Table 8-1 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.

Table 8-1 ALGORITHM_CONFIGURATION Registers
OffsetAcronymRegister NameSection
80hISD_CONFIGISD ConfigurationSection 8.1.1
82hREV_DRIVE_CONFIGReverse Drive ConfigurationSection 8.1.2
84hMOTOR_STARTUP1Motor Startup Configuration1Section 8.1.3
86hMOTOR_STARTUP2Motor Startup Configuration2Section 8.1.4
88hCLOSED_LOOP1Close Loop Configuration1Section 8.1.5
8AhCLOSED_LOOP2Close Loop Configuration2Section 8.1.6
8ChCLOSED_LOOP3Close Loop Configuration3Section 8.1.7
8EhCLOSED_LOOP4Close Loop Configuration4Section 8.1.8
94hREF_PROFILES1Reference Profile Configuration1Section 8.1.9
96hREF_PROFILES2Reference Profile Configuration2Section 8.1.10
98hREF_PROFILES3Reference Profile Configuration3Section 8.1.11
9AhREF_PROFILES4Reference Profile Configuration4Section 8.1.12
9ChREF_PROFILES5Reference Profile Configuration5Section 8.1.13
9EhREF_PROFILES6Reference Profile Configuration6Section 8.1.14

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 Algorithm_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in Figure 8-1 and described in Table 8-3.

Return to the Summary Table.

Register to configure initial speed detect settings

Figure 8-1 ISD_CONFIG Register
3130292827262524
PARITYISD_ENBRAKE_ENHIZ_ENRVS_DR_ENRESYNC_ENFW_DRV_RESYN_THR
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
FW_DRV_RESYN_THRISD_BEMF_FILT_ENABLESINGLE_SHUNT_BLANKING_TIMEBRK_TIME
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BRK_TIMEHIZ_TIMESTAT_DETECT_THR
R/W-0hR/W-0hR/W-0h
76543210
STAT_DETECT_THRREV_DRV_HANDOFF_THRREV_DRV_OPEN_LOOP_CURRENT
R/W-0hR/W-0hR/W-0h
Table 8-3 ISD_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30ISD_ENR/W0h ISD enable during MSS
  • 0h = Disable
  • 1h = Enable
29BRAKE_ENR/W0h Brake enable during MSS
  • 0h = Disable
  • 1h = Enable
28HIZ_ENR/W0h Hi-Z enable during MSS
  • 0h = Disable
  • 1h = Enable
27RVS_DR_ENR/W0h Reverse drive operation enable during MSS
  • 0h = Disable
  • 1h = Enable
26RESYNC_ENR/W0h Resynchronization enable during MSS
  • 0h = Disable
  • 1h = Enable
25-22FW_DRV_RESYN_THRR/W0h Minimum speed threshold for resynchronize to closed loop (% of MAX_SPEED)
  • 0h = 5%
  • 1h = 10%
  • 2h = 15%
  • 3h = 20%
  • 4h = 25%
  • 5h = 30%
  • 6h = 35%
  • 7h = 40%
  • 8h = 45%
  • 9h = 50%
  • Ah = Not Applicable
  • Bh = Not Applicable
  • Ch = Not Applicable
  • Dh = Not Applicable
  • Eh = Not Applicable
  • Fh = Not Applicable
21ISD_BEMF_FILT_ENABLER/W0h BEMF filter enable during ISD
  • 0h = Disable
  • 1h = Enable
20-17SINGLE_SHUNT_BLANKING_TIMER/W0h Blanking time before current sampling from the PWM edge
  • 0h = 0.25 µs
  • 1h = 0.5 µs
  • 2h = 0.75 µs
  • 3h = 1 µs
  • 4h = 1.25 µs
  • 5h = 1.5 µs
  • 6h = 1.75 µs
  • 7h = 2 µs
  • 8h = 2.25 µs
  • 9h = 2.5 µs
  • Ah = 2.75 µs
  • Bh = 3 µs
  • Ch = 3.5 µs
  • Dh = 4 µs
  • Eh = 5 µs
  • Fh = 6 µs
16-13BRK_TIMER/W0h Brake time during MSS
  • 0h = 10 ms
  • 1h = 50 ms
  • 2h = 100 ms
  • 3h = 200 ms
  • 4h = 300 ms
  • 5h = 400 ms
  • 6h = 500 ms
  • 7h = 750 ms
  • 8h = 1 s
  • 9h = 2 s
  • Ah = 3 s
  • Bh = 4 s
  • Ch = 5 s
  • Dh = 7.5 s
  • Eh = 10 s
  • Fh = 15 s
12-9HIZ_TIMER/W0h Hi-Z time during MSS
  • 0h = 10 ms
  • 1h = 50 ms
  • 2h = 100 ms
  • 3h = 200 ms
  • 4h = 300 ms
  • 5h = 400 ms
  • 6h = 500 ms
  • 7h = 750 ms
  • 8h = 1 s
  • 9h = 2 s
  • Ah = 3 s
  • Bh = 4 s
  • Ch = 5 s
  • Dh = 7.5 s
  • Eh = 10 s
  • Fh = 15 s
8-6STAT_DETECT_THRR/W0h BEMF threshold to detect if motor is stationary
  • 0h = 100 mV
  • 1h = 150 mV
  • 2h = 200 mV
  • 3h = 500 mV
  • 4h = 1000 mV
  • 5h = 1500 mV
  • 6h = 2000 mV
  • 7h = 3000 mV
5-3REV_DRV_HANDOFF_THRR/W0h Speed threshold for transitioning to open-loop during reverse drive (% of MAX_SPEED)
  • 0h = 5%
  • 1h = 10%
  • 2h = 15%
  • 3h = 20%
  • 4h = 25%
  • 5h = 30%
  • 6h = 40%
  • 7h = 50%
2-0REV_DRV_OPEN_LOOP_CURRENTR/W0h Open loop current limit during reverse drive (% of BASE_CURRENT)
  • 0h = 5%
  • 1h = 10%
  • 2h = 15%
  • 3h = 20%
  • 4h = 25%
  • 5h = 30%
  • 6h = 40%
  • 7h = 50%

8.1.2 REV_DRIVE_CONFIG Register (Offset = 82h) [Reset = 00000000h]

REV_DRIVE_CONFIG is shown in Figure 8-2 and described in Table 8-4.

Return to the Summary Table.

Register to configure reverse drive settings

Figure 8-2 REV_DRIVE_CONFIG Register
3130292827262524
PARITYREV_DRV_OPEN_LOOP_ACCEL_A1BUS_CURRENT_LIMIT_EN_MIN_VOLTAGE
R-0hR/W-0hR/W-0h
2322212019181716
BUS_CURRENT_LIMIT_EN_MIN_VOLTAGEACTIVE_BRAKE_CURRENT_LIMITACTIVE_BRAKE_KP
R/W-0hR/W-0hR/W-0h
15141312111098
ACTIVE_BRAKE_KPACTIVE_BRAKE_KI
R/W-0hR/W-0h
76543210
ACTIVE_BRAKE_KI
R/W-0h
Table 8-4 REV_DRIVE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-27REV_DRV_OPEN_LOOP_ACCEL_A1R/W0h Open loop acceleration coefficient A1 during reverse drive
  • 0h = 0.1 Hz/s
  • 1h = 0.5 Hz/s
  • 2h = 1 Hz/s
  • 3h = 2.5 Hz/s
  • 4h = 5 Hz/s
  • 5h = 10 Hz/s
  • 6h = 25 Hz/s
  • 7h = 50 Hz/s
  • 8h = 75 Hz/s
  • 9h = 100 Hz/s
  • Ah = 250 Hz/s
  • Bh = 500 Hz/s
  • Ch = 750 Hz/s
  • Dh = 1000 Hz/s
  • Eh = 5000 Hz/s
  • Fh = 10000 Hz/s
26-23BUS_CURRENT_LIMIT_EN_MIN_VOLTAGER/W0h Minimum PVDD voltage below which bus current limit is enabled (Applicable only if CTRL_MODE = 1h or BUS_POWER_LIMIT_ENABLE = 1)
  • 0h = Bus current Limit is disabled
  • 1h = 9 V
  • 2h = 10 V
  • 3h = 11 V
  • 4h = 12 V
  • 5h = 18 V
  • 6h = 20 V
  • 7h = 22 V
  • 8h = 24 V
  • 9h = 30 V
  • Ah = 32 V
  • Bh = 34 V
  • Ch = 36 V
  • Dh = 40 V
  • Eh = 44 V
  • Fh = 48 V
22-20ACTIVE_BRAKE_CURRENT_LIMITR/W0h Bus current limit during active braking (% of BASE_CURRENT)
  • 0h = 10%
  • 1h = 20%
  • 2h = 30%
  • 3h = 40%
  • 4h = 50%
  • 5h = 60%
  • 6h = 70%
  • 7h = 80%
19-10ACTIVE_BRAKE_KPR/W0h 10-bit value for active braking PI loop Kp.
Kp = ACTIVE_BRAKE_KP / 27
9-0ACTIVE_BRAKE_KIR/W0h 10-bit value for active braking PI loop Ki.
Ki = ACTIVE_BRAKE_KI / 29

8.1.3 MOTOR_STARTUP1 Register (Offset = 84h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in Figure 8-3 and described in Table 8-5.

Return to the Summary Table.

Register to configure motor startup settings1

Figure 8-3 MOTOR_STARTUP1 Register
3130292827262524
PARITYMTR_STARTUPALIGN_SLOW_RAMP_RATEALIGN_TIME
R-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ALIGN_TIMEALIGN_OR_SLOW_CURRENT_ILIMITRESERVED
R/W-0hR/W-0hR-0h
15141312111098
RESERVEDIPD_CURR_THRRESERVED
R-0hR/W-0hR-0h
76543210
IPD_ADV_ANGLEIPD_REPEATRESERVEDIQ_RAMP_DOWN_ENACTIVE_BRAKE_ENRESERVED
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR-0h
Table 8-5 MOTOR_STARTUP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-29MTR_STARTUPR/W0h Motor startup mode
  • 0h = Align
  • 1h = Double Align
  • 2h = IPD
  • 3h = Slow first cycle
28-25ALIGN_SLOW_RAMP_RATER/W0h Align, slow first cycle and open loop current ramp rate
  • 0h = 1 A/s
  • 1h = 5 A/s
  • 2h = 10 A/s
  • 3h = 25 A/s
  • 4h = 50 A/s
  • 5h = 100 A/s
  • 6h = 150 A/s
  • 7h = 250 A/s
  • 8h = 500 A/s
  • 9h = 1000 A/s
  • Ah = 2000 A/s
  • Bh = 5000 A/s
  • Ch = 10000 A/s
  • Dh = 20000 A/s
  • Eh = 50000 A/s
  • Fh = No Limit A/s
24-21ALIGN_TIMER/W0h Align time
  • 0h = 10 ms
  • 1h = 50 ms
  • 2h = 100 ms
  • 3h = 200 ms
  • 4h = 300 ms
  • 5h = 400 ms
  • 6h = 500 ms
  • 7h = 750 ms
  • 8h = 1 s
  • 9h = 1.5 s
  • Ah = 2 s
  • Bh = 3 s
  • Ch = 4 s
  • Dh = 5 s
  • Eh = 7.5 s
  • Fh = 10 s
20-17ALIGN_OR_SLOW_CURRENT_ILIMITR/W0h Align or slow first cycle current limit (% of BASE_CURRENT)
  • 0h = 5%
  • 1h = 10%
  • 2h = 15%
  • 3h = 20%
  • 4h = 25%
  • 5h = 30%
  • 6h = 40%
  • 7h = 45%
  • 8h = 50%
  • 9h = 55%
  • Ah = 60%
  • Bh = 65%
  • Ch = 70%
  • Dh = 75%
  • Eh = 80%
  • Fh = 85%
16-14RESERVEDR0h Reserved
13-10IPD_CURR_THRR/W0h IPD current threshold (% of BASE_CURRENT)
  • 0h = Not Applicable
  • 1h = Not Applicable
  • 2h = Not Applicable
  • 3h = 20%
  • 4h = 26.7%
  • 5h = 33.3%
  • 6h = 40%
  • 7h = 46.7%
  • 8h = 53.3%
  • 9h = 60%
  • Ah = 66.7%
  • Bh = 73.3%
  • Ch = 80%
  • Dh = 86.7%
  • Eh = 93.3%
  • Fh = 100%
9-8RESERVEDR0h Reserved
7-6IPD_ADV_ANGLER/W0h IPD advance angle
  • 0h = 0°
  • 1h = 30°
  • 2h = 60°
  • 3h = 90°
5-4IPD_REPEATR/W0h Number of times IPD is executed
  • 0h = 1 time
  • 1h = average of 2 times
  • 2h = average of 3 times
  • 3h = average of 4 times
3RESERVEDR0h Reserved
2IQ_RAMP_DOWN_ENR/W0h Q-axis current ramp-down enable during open-loop to closed-loop transition
  • 0h = Disable
  • 1h = Enable
1ACTIVE_BRAKE_ENR/W0h Active braking enable during deceleration
  • 0h = Disable
  • 1h = Enable
0RESERVEDR0h Reserved

8.1.4 MOTOR_STARTUP2 Register (Offset = 86h) [Reset = 00000000h]

MOTOR_STARTUP2 is shown in Figure 8-4 and described in Table 8-6.

Return to the Summary Table.

Register to configure motor startup settings2

Figure 8-4 MOTOR_STARTUP2 Register
3130292827262524
PARITYOL_ILIMITOL_ACC_A1
R-0hR/W-0hR/W-0h
2322212019181716
OL_ACC_A1OL_ACC_A2AUTO_HANDOFF_ENOPN_CL_HANDOFF_THR
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
OPN_CL_HANDOFF_THRSTANDBY_POWERAUTO_HANDOFF_MIN_BEMF
R/W-0hR/W-0hR/W-0h
76543210
SLOW_FIRST_CYC_FREQRESERVEDTHETA_ERROR_RAMP_RATE
R/W-0hR-0hR/W-0h
Table 8-6 MOTOR_STARTUP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-27OL_ILIMITR/W0h Open-loop current limit (% of BASE_CURRENT)
  • 0h = 5%
  • 1h = 10%
  • 2h = 15%
  • 3h = 20%
  • 4h = 25%
  • 5h = 30%
  • 6h = 40%
  • 7h = 45%
  • 8h = 50%
  • 9h = 55%
  • Ah = 60%
  • Bh = 65%
  • Ch = 70%
  • Dh = 75%
  • Eh = 80%
  • Fh = 85%
26-23OL_ACC_A1R/W0h Open loop acceleration coefficient A1
  • 0h = 0.1 Hz/s
  • 1h = 0.5 Hz/s
  • 2h = 1 Hz/s
  • 3h = 2.5 Hz/s
  • 4h = 5 Hz/s
  • 5h = 10 Hz/s
  • 6h = 25 Hz/s
  • 7h = 50 Hz/s
  • 8h = 75 Hz/s
  • 9h = 100 Hz/s
  • Ah = 250 Hz/s
  • Bh = 500 Hz/s
  • Ch = 750 Hz/s
  • Dh = 1000 Hz/s
  • Eh = 5000 Hz/s
  • Fh = 10000 Hz/s
22-19OL_ACC_A2R/W0h Open loop acceleration coefficient A2
  • 0h = 0 Hz/s²
  • 1h = 0.5 Hz/s²
  • 2h = 1 Hz/s²
  • 3h = 2.5 Hz/s²
  • 4h = 5 Hz/s²
  • 5h = 10 Hz/s²
  • 6h = 25 Hz/s²
  • 7h = 50 Hz/s²
  • 8h = 75 Hz/s²
  • 9h = 100 Hz/s²
  • Ah = 250 Hz/s²
  • Bh = 500 Hz/s²
  • Ch = 750 Hz/s²
  • Dh = 1000 Hz/s²
  • Eh = 5000 Hz/s²
  • Fh = 10000 Hz/s²
18AUTO_HANDOFF_ENR/W0h Auto handoff enable for open loop to closed loop transition
  • 0h = Disable
  • 1h = Enable
17-13OPN_CL_HANDOFF_THRR/W0h Open-loop to closed-loop handoff threshold (% of MAX_SPEED)
  • 0h = 1%
  • 1h = 2%
  • 2h = 3%
  • 3h = 4%
  • 4h = 5%
  • 5h = 6%
  • 6h = 7%
  • 7h = 8%
  • 8h = 9%
  • 9h = 10%
  • Ah = 11%
  • Bh = 12%
  • Ch = 13%
  • Dh = 14%
  • Eh = 15%
  • Fh = 16%
  • 10h = 17%
  • 11h = 18%
  • 12h = 19%
  • 13h = 20%
  • 14h = 22.5%
  • 15h = 25%
  • 16h = 27.5%
  • 17h = 30%
  • 18h = 32.5%
  • 19h = 35%
  • 1Ah = 37.5%
  • 1Bh = 40%
  • 1Ch = 42.5%
  • 1Dh = 45%
  • 1Eh = 47.5%
  • 1Fh = 50%
12-11STANDBY_POWERR/W0h Standby board power consumption (when motor is not driven)
  • 0h = 0.5 W
  • 1h = 1 W
  • 2h = 2 W
  • 3h = 4 W
10-8AUTO_HANDOFF_MIN_BEMFR/W0h Minimum BEMF threshold required for auto handoff
  • 0h = 0 mV
  • 1h = 100 mV
  • 2h = 200 mV
  • 3h = 500 mV
  • 4h = 1000 mV
  • 5h = 2000 mV
  • 6h = 2500 mV
  • 7h = 3000 mV
7-4SLOW_FIRST_CYC_FREQR/W0h First cycle frequency in slow first cycle startup (% of MAX_SPEED)
  • 0h = 0.1%
  • 1h = 0.3%
  • 2h = 0.5%
  • 3h = 0.7%
  • 4h = 1%
  • 5h = 1.5%
  • 6h = 2%
  • 7h = 2.5%
  • 8h = 3%
  • 9h = 4%
  • Ah = 5%
  • Bh = 7.5%
  • Ch = 10%
  • Dh = 15%
  • Eh = 20%
  • Fh = 25%
3RESERVEDR0h Reserved
2-0THETA_ERROR_RAMP_RATER/W0h Ramp rate for reducing difference between estimated angle and open loop angle during open loop to closed loop transition
  • 0h = 0.01 deg/ms
  • 1h = 0.05 deg/ms
  • 2h = 0.1 deg/ms
  • 3h = 0.2 deg/ms
  • 4h = 0.5 deg/ms
  • 5h = 1 deg/ms
  • 6h = 2 deg/ms
  • 7h = 4 deg/ms

8.1.5 CLOSED_LOOP1 Register (Offset = 88h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in Figure 8-5 and described in Table 8-7.

Return to the Summary Table.

Register to configure close loop settings1

Figure 8-5 CLOSED_LOOP1 Register
3130292827262524
PARITYOVERMODULATION_ENABLECL_ACCRESERVED
R-0hR/W-0hR/W-0hR-0h
2322212019181716
CL_DECPWM_FREQ_OUT
R/W-0hR/W-0h
15141312111098
PWM_FREQ_OUTESTIMATOR_FILT_ENFG_SELFG_DIV
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
FG_CONFIGFG_BEMF_THRAVS_ENRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR-0hR-0hR-0h
Table 8-7 CLOSED_LOOP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30OVERMODULATION_ENABLER/W0h Over-modulation enable
  • 0h = Disable
  • 1h = Enable
29-25CL_ACCR/W0h Closed loop acceleration
Speed control (Hz/s)
Power control (W/s)
Current control (0.1A/s)
Modulation index control(0.01% modulation index/s)
  • 0h = 0.5
  • 1h = 1
  • 2h = 2.5
  • 3h = 5
  • 4h = 7.5
  • 5h = 10
  • 6h = 20
  • 7h = 40
  • 8h = 60
  • 9h = 80
  • Ah = 100
  • Bh = 200
  • Ch = 300
  • Dh = 400
  • Eh = 500
  • Fh = 600
  • 10h = 700
  • 11h = 800
  • 12h = 1000
  • 13h = 1250
  • 14h = 1500
  • 15h = 2000
  • 16h = 2500
  • 17h = 3000
  • 18h = 4000
  • 19h = 5000
  • 1Ah = 6000
  • 1Bh = 8000
  • 1Ch = 10000
  • 1Dh = 20000
  • 1Eh = 40000
  • 1Fh = No limit
24RESERVEDR0h Reserved
23-19CL_DECR/W0h Closed loop deceleration
Speed control (Hz/s)
Power control (W/s)
Current control (0.1A/s)
Modulation index control(0.01% modulation index/s)
  • 0h = 0.5
  • 1h = 1
  • 2h = 2.5
  • 3h = 5
  • 4h = 7.5
  • 5h = 10
  • 6h = 20
  • 7h = 40
  • 8h = 60
  • 9h = 80
  • Ah = 100
  • Bh = 200
  • Ch = 300
  • Dh = 400
  • Eh = 500
  • Fh = 600
  • 10h = 700
  • 11h = 800
  • 12h = 1000
  • 13h = 1250
  • 14h = 1500
  • 15h = 2000
  • 16h = 2500
  • 17h = 3000
  • 18h = 4000
  • 19h = 5000
  • 1Ah = 6000
  • 1Bh = 8000
  • 1Ch = 10000
  • 1Dh = 20000
  • 1Eh = 40000
  • 1Fh = No limit
18-15PWM_FREQ_OUTR/W0h PWM output frequency
  • 0h = 10 kHz
  • 1h = 15 kHz
  • 2h = 20 kHz
  • 3h = 25 kHz
  • 4h = 30 kHz
  • 5h = 35 kHz
  • 6h = 40 kHz
  • 7h = 45 kHz
  • 8h = 50 kHz
  • 9h = 55 kHz
  • Ah = 60 kHz
  • Bh = 65 kHz
  • Ch = 70 kHz
  • Dh = 75 kHz
  • Eh = 80 kHz
  • Fh = Not Applicable
14ESTIMATOR_FILT_ENR/W0h Estimator filter enable (Note: May introduce control response delay)
  • 0h = Disable
  • 1h = Enable
13-12FG_SELR/W0h Configure motor states when speed feedback is available on FG
  • 0h = Output FG in ISD, open loop and closed loop
  • 1h = Output FG in only closed loop
  • 2h = Output FG in open loop for the first try
  • 3h = Not Defined
11-8FG_DIVR/W0h FG division factor
  • 0h = Commutation cycle, 3x of electrical
  • 1h = Divide by 1 (2-pole motor mechanical speed)
  • 2h = Divide by 2 (4-pole motor mechanical speed)
  • 3h = Divide by 3 (6-pole motor mechanical speed)
  • 4h = Divide by 4 (8-pole motor mechanical speed)
  • 5h = Divide by 5 (10-pole motor mechanical speed)
  • 6h = Divide by 6 (12-pole motor mechanical speed)
  • 7h = Divide by 7 (14-pole motor mechanical speed)
  • 8h = Divide by 8 (16-pole motor mechanical speed)
  • 9h = Divide by 9 (18-pole motor mechanical speed)
  • Ah = Divide by 10 (20-pole motor mechanical speed)
  • Bh = Divide by 11 (22-pole motor mechanical speed)
  • Ch = Divide by 12 (24-pole motor mechanical speed)
  • Dh = Divide by 13 (26-pole motor mechanical speed)
  • Eh = Divide by 14 (28-pole motor mechanical speed)
  • Fh = Divide by 15 (30-pole motor mechanical speed)
7FG_CONFIGR/W0h FG output configuration
  • 0h = FG active as long as motor is driven
  • 1h = FG active till BEMF drops below BEMF threshold defined by FG_BEMF_THR
6-4FG_BEMF_THRR/W0h BEMF threshold above which speed feedback information is available on FG, calculated as voltage at SHx pin divided by voltage gain(refer BUS_VOLT).
  • 0h = ±1 mV
  • 1h = ±2 mV
  • 2h = ±5 mV
  • 3h = ±10 mV
  • 4h = ±20 mV
  • 5h = ±30 mV
  • 6h = Not Applicable
  • 7h = Not Applicable
3AVS_ENR/W0h AVS enable
  • 0h = Disable
  • 1h = Enable
2RESERVEDR0h Reserved
1RESERVEDR0h Reserved
0RESERVEDR0h Reserved

8.1.6 CLOSED_LOOP2 Register (Offset = 8Ah) [Reset = 00000000h]

CLOSED_LOOP2 is shown in Figure 8-6 and described in Table 8-8.

Return to the Summary Table.

Register to configure close loop settings2

Figure 8-6 CLOSED_LOOP2 Register
3130292827262524
PARITYRESERVEDMTR_STOPMTR_STOP_BRK_TIME
R-0hR-0hR/W-0hR/W-0h
2322212019181716
ACT_SPIN_THRBRAKE_SPEED_THRESHOLD
R/W-0hR/W-0h
15141312111098
MOTOR_RES
R/W-0h
76543210
MOTOR_IND
R/W-0h
Table 8-8 CLOSED_LOOP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30RESERVEDR0h Reserved
29-28MTR_STOPR/W0h Motor stop mode
  • 0h = Hi-Z
  • 1h = Low side braking
  • 2h = Active spin down
  • 3h = Reserved
27-24MTR_STOP_BRK_TIMER/W0h Brake time during motor stop
  • 0h = 10 ms
  • 1h = 50 ms
  • 2h = 100 ms
  • 3h = 200 ms
  • 4h = 300 ms
  • 5h = 400 ms
  • 6h = 500 ms
  • 7h = 750 ms
  • 8h = 1 s
  • 9h = 2 s
  • Ah = 3 s
  • Bh = 4 s
  • Ch = 5 s
  • Dh = 7.5 s
  • Eh = 10 s
  • Fh = 15 s
23-20ACT_SPIN_THRR/W0h Active spin-down speed threshold (% of MAX_SPEED)
  • 0h = 100%
  • 1h = 90%
  • 2h = 80%
  • 3h = 70%
  • 4h = 60%
  • 5h = 50%
  • 6h = 45%
  • 7h = 40%
  • 8h = 35%
  • 9h = 30%
  • Ah = 25%
  • Bh = 20%
  • Ch = 15%
  • Dh = 10%
  • Eh = Not Applicable
  • Fh = Not Applicable
19-16BRAKE_SPEED_THRESHOLDR/W0h Speed threshold below which brake is applied for BRAKE pin and Motor stop mode (Low side Braking) (% of MAX_SPEED)
  • 0h = 100%
  • 1h = 90%
  • 2h = 80%
  • 3h = 70%
  • 4h = 60%
  • 5h = 50%
  • 6h = 45%
  • 7h = 40%
  • 8h = 35%
  • 9h = 30%
  • Ah = 25%
  • Bh = 20%
  • Ch = 15%
  • Dh = 10%
  • Eh = Not Applicable
  • Fh = Not Applicable
15-8MOTOR_RESR/W0h Motor phase resistance
7-0MOTOR_INDR/W0h Motor phase inductance

8.1.7 CLOSED_LOOP3 Register (Offset = 8Ch) [Reset = 00000000h]

CLOSED_LOOP3 is shown in Figure 8-7 and described in Table 8-9.

Return to the Summary Table.

Register to configure close loop settings3

Figure 8-7 CLOSED_LOOP3 Register
3130292827262524
PARITYMOTOR_BEMF_CONST
R-0hR/W-0h
2322212019181716
MOTOR_BEMF_CONSTCURR_LOOP_KP
R/W-0hR/W-0h
15141312111098
CURR_LOOP_KPCURR_LOOP_KI
R/W-0hR/W-0h
76543210
CURR_LOOP_KISPD_LOOP_KP
R/W-0hR/W-0h
Table 8-9 CLOSED_LOOP3 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-23MOTOR_BEMF_CONSTR/W0h Motor BEMF constant
22-13CURR_LOOP_KPR/W0h 10-bit Kp value for Q-axis and D-axis current PI loop.
CURR_LOOP_KP is divided in 2 sections - SCALE(9:8) and VALUE(7:0).
Kp = VALUE / 10^SCALE
Set to 0 for auto calculation of current Kp and Ki
12-3CURR_LOOP_KIR/W0h 10-bit Ki value for Q-axis and D-axis current PI loop.
CURR_LOOP_KI is divided in 2 sections - SCALE(9:8) and VALUE(7:0).
Ki = 1000 × VALUE / 10^SCALE
Set to 0 for auto calculation of current Kp and Ki
2-0SPD_LOOP_KPR/W0h 3 MSB bits for speed loop/power loop Kp.
SPD_LOOP_KP is divided in 2 sections - SCALE(9:8) and VALUE(7:0).
Kp = 0.01 × VALUE / 10^SCALE.

8.1.8 CLOSED_LOOP4 Register (Offset = 8Eh) [Reset = 00000000h]

CLOSED_LOOP4 is shown in Figure 8-8 and described in Table 8-10.

Return to the Summary Table.

Register to configure close loop settings4

Figure 8-8 CLOSED_LOOP4 Register
3130292827262524
PARITYSPD_LOOP_KP
R-0hR/W-0h
2322212019181716
SPD_LOOP_KI
R/W-0h
15141312111098
SPD_LOOP_KIMAX_SPEED
R/W-0hR/W-0h
76543210
MAX_SPEED
R/W-0h
Table 8-10 CLOSED_LOOP4 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-24SPD_LOOP_KPR/W0h 7 LSB bits for speed loop/power loop Kp.
SPD_LOOP_KP is divided in 2 sections - SCALE(10:9) and VALUE(8:0).
Kp = 0.01 × VALUE / 10^SCALE.
23-14SPD_LOOP_KIR/W0h 10 bit value for speed loop/power loop Ki.
SPD_LOOP_KI is divided in 2 sections - SCALE(9:8) and VALUE(7:0).
Ki = 0.1 × VALUE / 10^SCALE.
13-0MAX_SPEEDR/W0h Maximum motor speed in electrical Hz = MAX_SPEED/4
For example, if MAX_SPEED is 0x7D0(2000d), then maximum motor speed (Hz) is 2000/4 = 500Hz

8.1.9 REF_PROFILES1 Register (Offset = 94h) [Reset = 00000000h]

REF_PROFILES1 is shown in Figure 8-9 and described in Table 8-11.

Return to the Summary Table.

Register to configure reference profile1

Figure 8-9 REF_PROFILES1 Register
3130292827262524
PARITYREF_PROFILE_CONFIGDUTY_ON1
R-0hR/W-0hR/W-0h
2322212019181716
DUTY_ON1DUTY_OFF1
R/W-0hR/W-0h
15141312111098
DUTY_OFF1DUTY_CLAMP1
R/W-0hR/W-0h
76543210
DUTY_CLAMP1DUTY_A
R/W-0hR/W-0h
Table 8-11 REF_PROFILES1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-29REF_PROFILE_CONFIGR/W0h Reference profile mode configuration
  • 0h = Reference mode
  • 1h = Linear mode
  • 2h = Staircase mode
  • 3h = Forward Reverse mode
28-21DUTY_ON1R/W0h Duty_ON1 Configuration
Turn On duty cycle (%) = {(DUTY_ON1/256) × 100}
20-13DUTY_OFF1R/W0h Duty_OFF1 Configuration
Turn Off duty cycle (%) = {(DUTY_OFF1/256) × 100}
12-5DUTY_CLAMP1R/W0h Duty_CLAMP1 Configuration
duty cycle for clamping (%) = {(DUTY_CLAMP1/256) ×100}
4-0DUTY_AR/W0h 5 MSB bits for Duty Cycle A

8.1.10 REF_PROFILES2 Register (Offset = 96h) [Reset = 00000000h]

REF_PROFILES2 is shown in Figure 8-10 and described in Table 8-12.

Return to the Summary Table.

Register to configure reference profile2

Figure 8-10 REF_PROFILES2 Register
3130292827262524
PARITYDUTY_ADUTY_B
R-0hR/W-0hR/W-0h
2322212019181716
DUTY_BDUTY_C
R/W-0hR/W-0h
15141312111098
DUTY_CDUTY_D
R/W-0hR/W-0h
76543210
DUTY_DDUTY_E
R/W-0hR/W-0h
Table 8-12 REF_PROFILES2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-28DUTY_AR/W0h 3 LSB bits for Duty Cycle A Configuration
Duty Cycle A (%) = {(DUTY_A/256) × 100}
27-20DUTY_BR/W0h Duty_B Configuration
Duty cycle B (%) = {(DUTY_B/256) × 100}
19-12DUTY_CR/W0h Duty_C Configuration
Duty cycle C (%) = {(DUTY_C/256) × 100}
11-4DUTY_DR/W0h Duty_D Configuration
Duty cycle D (%) = {(DUTY_D/256) × 100}
3-0DUTY_ER/W0h 4 MSB bits for Duty Cycle E

8.1.11 REF_PROFILES3 Register (Offset = 98h) [Reset = 00000000h]

REF_PROFILES3 is shown in Figure 8-11 and described in Table 8-13.

Return to the Summary Table.

Register to configure reference profile3

Figure 8-11 REF_PROFILES3 Register
3130292827262524
PARITYDUTY_EDUTY_ON2
R-0hR/W-0hR/W-0h
2322212019181716
DUTY_ON2DUTY_OFF2
R/W-0hR/W-0h
15141312111098
DUTY_OFF2DUTY_CLAMP2
R/W-0hR/W-0h
76543210
DUTY_CLAMP2DUTY_HYSRESERVED
R/W-0hR/W-0hR-0h
Table 8-13 REF_PROFILES3 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-27DUTY_ER/W0h 4 LSB bits for Duty Cycle E Configuration
Duty cycle E (%) = {(DUTY_E/256) × 100}
26-19DUTY_ON2R/W0h Duty_ON2 Configuration
Turn On duty cycle (%) = {(DUTY_ON2/256) × 100}
18-11DUTY_OFF2R/W0h Duty_OFF2 Configuration
Turn Off duty cycle (%) = {(DUTY_OFF2/256) × 100}
10-3DUTY_CLAMP2R/W0h Duty_CLAMP2 Configuration
Duty cycle for clamping (%) = {(DUTY_CLAMP2/256) × 100}
2-1DUTY_HYSR/W0h Input duty hysteresis
  • 0h = 0%
  • 1h = 1%
  • 2h = 2%
  • 3h = 3%
0RESERVEDR0h Reserved

8.1.12 REF_PROFILES4 Register (Offset = 9Ah) [Reset = 00000000h]

REF_PROFILES4 is shown in Figure 8-12 and described in Table 8-14.

Return to the Summary Table.

Register to configure reference profile4

Figure 8-12 REF_PROFILES4 Register
3130292827262524
PARITYREF_OFF1
R-0hR/W-0h
2322212019181716
REF_OFF1REF_CLAMP1
R/W-0hR/W-0h
15141312111098
REF_CLAMP1REF_A
R/W-0hR/W-0h
76543210
REF_AREF_B
R/W-0hR/W-0h
Table 8-14 REF_PROFILES4 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-23REF_OFF1R/W0h Turn off ref Configuration
Turn off reference (% of Maximum Reference) = {(REF_OFF1/256) × 100}
22-15REF_CLAMP1R/W0h Ref Clamp1 Configuration
Clamp ref (% of Maximum Reference) = {(REF_CLAMP1/256) × 100}
14-7REF_AR/W0h Ref A configuration
Ref A (% of Maximum Reference) = {(REF_A/256) × 100}
6-0REF_BR/W0h 7 MSB of REF_B configuration

8.1.13 REF_PROFILES5 Register (Offset = 9Ch) [Reset = 00000000h]

REF_PROFILES5 is shown in Figure 8-13 and described in Table 8-15.

Return to the Summary Table.

Register to configure reference profile5

Figure 8-13 REF_PROFILES5 Register
3130292827262524
PARITYREF_BREF_C
R-0hR/W-0hR/W-0h
2322212019181716
REF_CREF_D
R/W-0hR/W-0h
15141312111098
REF_DREF_E
R/W-0hR/W-0h
76543210
REF_EMIN_DUTYMIXED_MODE_CONFIGDUTY_COMMAND_FILTERRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 8-15 REF_PROFILES5 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30REF_BR/W0h 1 LSB of REF_B configuration
Ref B(% of Maximum Reference) = {(REF_B/256) × 100}
29-22REF_CR/W0h Ref C configuration
Ref C (% of Maximum Reference) = {(REF_C/256) × 100}
21-14REF_DR/W0h Ref D configuration
Ref D (% of Maximum Reference) = {(REF_D/256) × 100}
13-6REF_ER/W0h Ref E Configuration
Ref E(% of Maximum Reference) = {(REF_E/256)*100}
5-4MIN_DUTYR/W0h Minimum input duty threshold above which motor start (Applicable only if REF_PROFILE_CONFIG = 0h)
  • 0h = 1%
  • 1h = 3%
  • 2h = 5%
  • 3h = 10%
3-2MIXED_MODE_CONFIGR/W0h Mixed control mode configuration(Applicable only if REF_PROFILE_CONFIG = 1h or REF_PROFILE_CONFIG = 2h)
  • 0h = User defined reference modes throughout the input duty range
  • 1h = Modulation index control if input duty > DUTY_C + DUTY_HYST; configured CTRL_MODE if input duty < DUTY_C - DUTY_HYST
  • 2h = configured CTRL_MODE if input duty > DUTY_C + DUTY_HYST; Modulation index control if input duty < DUTY_C - DUTY_HYST
  • 3h = Not Applicable
1DUTY_COMMAND_FILTERR/W0h Input duty filter
  • 0h = Filter on input duty is disabled
  • 1h = Filter on input duty is enabled (0.4%)
0RESERVEDR0h Reserved

8.1.14 REF_PROFILES6 Register (Offset = 9Eh) [Reset = 00000000h]

REF_PROFILES6 is shown in Figure 8-14 and described in Table 8-16.

Return to the Summary Table.

Register to configure reference profile6

Figure 8-14 REF_PROFILES6 Register
3130292827262524
PARITYREF_OFF2
R-0hR/W-0h
2322212019181716
REF_OFF2REF_CLAMP2
R/W-0hR/W-0h
15141312111098
REF_CLAMP2HALL_ANGLE_REFRESERVED
R/W-0hR/W-0hR-0h
76543210
RESERVED
R-0h
Table 8-16 REF_PROFILES6 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-23REF_OFF2R/W0h Turn off Ref Configuration
Turn off Ref (% of Maximum Reference)) = {(REF_OFF2/256) × 100}
22-15REF_CLAMP2R/W0h Clamp Ref Configuration
Clamp Ref (% of Maximum Reference) = {(REF_CLAMP2/256) ×100}
14-9HALL_ANGLE_REFR/W0h Hall sensor angle reference for offset calibration (degrees = HALL_ANGLE_REF × 360/63)
8-0RESERVEDR0h Reserved