SLLSFZ8 November   2025 MCF8329HS-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  Low-Side Current Sense Amplifier
      5. 7.3.5  Device Interface Modes
        1. 7.3.5.1 Interface - Control and Monitoring
        2. 7.3.5.2 I2C Interface
      6. 7.3.6  Motor Control Input Options
        1. 7.3.6.1 Analog-Mode Motor Control
        2. 7.3.6.2 PWM-Mode Motor Control
        3. 7.3.6.3 Frequency-Mode Motor Control
        4. 7.3.6.4 I2C based Motor Control
        5. 7.3.6.5 Input Control Signal Profiles
          1. 7.3.6.5.1 Linear Control Profiles
          2. 7.3.6.5.2 Staircase Control Profiles
          3. 7.3.6.5.3 Forward-Reverse Profiles
          4. 7.3.6.5.4 Multi-Reference Mode Operation
          5. 7.3.6.5.5 Input Reference Transfer Function without Profiler
      7. 7.3.7  Bootstrap Capacitor Initial Charging
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
          1. 7.3.9.3.1 Reverse Drive Tuning
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open Loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 Closed loop accelerate
        2. 7.3.10.2 Speed PI Control
        3. 7.3.10.3 Current PI Control
        4. 7.3.10.4 Overmodulation
        5. 7.3.10.5 Power Loop
        6. 7.3.10.6 Modulation Index Control
        7. 7.3.10.7 Motor Speed Limit
        8. 7.3.10.8 Input DC Power Limit
      11. 7.3.11 Maximum Torque Per Ampere (MTPA) Control
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Single Hall Sensor Operation
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Active Braking
      18. 7.3.18 Output PWM Switching Frequency
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behavior During Fault
      23. 7.3.23 Protections
        1. 7.3.23.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.23.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.23.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.23.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.23.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.23.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.23.7  Thermal Shutdown (OTSD)
        8. 7.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE = 111b)
        9. 7.3.23.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.23.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 111b)
        10. 7.3.23.10 Motor Lock (MTR_LCK)
          1. 7.3.23.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xb or 010b)
          2. 7.3.23.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE = 011b or 10xb)
          3. 7.3.23.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 110b)
          4. 7.3.23.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 111b)
        11. 7.3.23.11 Motor Lock Detection
          1. 7.3.23.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.23.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.23.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.23.12 MPET Faults
        13. 7.3.23.13 IPD Faults
        14. 7.3.23.14 Dry Run Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 Oscillator Source
      3. 7.5.3 External Watchdog with MCU Reset
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Algorithm_Control Registers
    4. 9.4 Device_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Typical Applications
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3.      Gate Drive Current
      4.      Gate Resistor Selection
      5.      System Considerations in High Power Designs
      6.      Capacitor Voltage Ratings
      7.      External Power Stage Components
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Bulk Capacitance
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Thermal Considerations
        1. 10.4.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

8.4 Internal_Algorithm_Configuration Registers

Table 8-29 lists the memory-mapped registers for the Internal_Algorithm_Configuration registers. All register offset addresses not listed in Table 8-29 should be considered as reserved locations and the register contents should not be modified.

Table 8-29 INTERNAL_ALGORITHM_CONFIGURATION Registers
OffsetAcronymRegister NameSection
A0hINT_ALGO_1Internal Algorithm Configuration1Section 8.4.1
A2hINT_ALGO_2Internal Algorithm Configuration2Section 8.4.2

Complex bit access types are encoded to fit into small table cells. Table 8-30 shows the codes that are used for access types in this section.

Table 8-30 Internal_Algorithm_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.4.1 INT_ALGO_1 Register (Offset = A0h) [Reset = 00000000h]

INT_ALGO_1 is shown in Figure 8-23 and described in Table 8-31.

Return to the Summary Table.

Register to configure internal algorithm parameters1

Figure 8-23 INT_ALGO_1 Register
3130292827262524
PARITYABNORMAL_BEMF_PERSISTENT_TIMESPEED_PIN_GLITCH_FILTERFAST_ISD_ENISD_STOP_TIME
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISD_RUN_TIMEISD_TIMEOUTDRY_RUN_TDEGDRY_RUN_ILIM_FIFTY_PERCENT_SPEED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DRY_RUN_ILIM_FIFTY_PERCENT_SPEEDDRY_RUN_ILIM
R/W-0hR/W-0h
76543210
DRY_RUN_SPEED_THRDRY_RUN_ILIM_MODEDRY_RUN_MODEREV_DRV_OPEN_LOOP_DEC
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-31 INT_ALGO_1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-29ABNORMAL_BEMF_PERSISTENT_TIMER/W0h Deglitch time for abnormal BEMF fault detection
  • 0h = 2 electrical cycles
  • 1h = 500 ms
  • 2h = 1000 ms
  • 3h = 2000 ms
28-27SPEED_PIN_GLITCH_FILTERR/W0h Glitch filter applied on SPEED/WAKE pin(Applicable when SPEED_MODE = 1h or SPEED_MODE =3h)
  • 0h = No Glitch Filter
  • 1h = 0.2 µs
  • 2h = 0.5 µs
  • 3h = 1.0 µs
26FAST_ISD_ENR/W0h Fast speed detection enable during ISD
  • 0h = Disable
  • 1h = Enable
25-24ISD_STOP_TIMER/W0h Persistence time for declaring motor has stopped during ISD
  • 0h = 1 ms
  • 1h = 5 ms
  • 2h = 50 ms
  • 3h = 100 ms
23-22ISD_RUN_TIMER/W0h Persistence time for declaring motor is running during ISD
  • 0h = 1 ms
  • 1h = 5 ms
  • 2h = 50 ms
  • 3h = 100 ms
21-20ISD_TIMEOUTR/W0h Timeout in case ISD is unable to reliably detect speed or direction
  • 0h = 500 ms
  • 1h = 750 ms
  • 2h = 1000 ms
  • 3h = 2000 ms
19-17DRY_RUN_TDEGR/W0h Dry run fault detection deglitch time
  • 0h = 10 s
  • 1h = 30 s
  • 2h = 1 min
  • 3h = 2 min
  • 4h = 3 min
  • 5h = 5 min
  • 6h = 10 min
  • 7h = 15 min
16-13DRY_RUN_ILIM_FIFTY_PERCENT_SPEEDR/W0h Current limit threshold for dry run detection at 50% of maximum speed (% of ILIMIT)
  • 0h = 5%
  • 1h = 7.5%
  • 2h = 10%
  • 3h = 12.5%
  • 4h = 15%
  • 5h = 17.5%
  • 6h = 20%
  • 7h = 22.5%
  • 8h = 25%
  • 9h = 27.5%
  • Ah = 30%
  • Bh = 32.5%
  • Ch = 35%
  • Dh = 40%
  • Eh = 45%
  • Fh = 50%
12-8DRY_RUN_ILIMR/W0h Current limit threshold for dry run detection (% of ILIMIT)
  • 0h = 2.5%
  • 1h = 5%
  • 2h = 7.5%
  • 3h = 10%
  • 4h = 12.5%
  • 5h = 15%
  • 6h = 17.5%
  • 7h = 20%
  • 8h = 22.5%
  • 9h = 25%
  • Ah = 27.5%
  • Bh = 30%
  • Ch = 32.5%
  • Dh = 35%
  • Eh = 37.5%
  • Fh = 40%
  • 10h = 42.5%
  • 11h = 45%
  • 12h = 47.5%
  • 13h = 50%
  • 14h = 52.5%
  • 15h = 55%
  • 16h = 57.5%
  • 17h = 60%
  • 18h = 62.5%
  • 19h = 65%
  • 1Ah = 67.5%
  • 1Bh = 70%
  • 1Ch = 72.5%
  • 1Dh = 75%
  • 1Eh = 77.5%
  • 1Fh = 80%
7-6DRY_RUN_SPEED_THRR/W0h Minimum speed threshold above which enable bit is active for dry run detection (% of MAX_SPEED)
  • 0h = 25%
  • 1h = 40%
  • 2h = 50%
  • 3h = 60%
5DRY_RUN_ILIM_MODER/W0h Dry run detection current limit mode
  • 0h = Current limit threshold is constant
  • 1h = Current limit threshold varies with speed
4-3DRY_RUN_MODER/W0h Dry run detection fault response mode
  • 0h = Dry run detection is disabled
  • 1h = Dry run detection fault is in report only but no action is taken; nFAULT active
  • 2h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
  • 3h = Dry run detection fault causes latched fault; nFAULT active; Gate driver is tristated
2-0REV_DRV_OPEN_LOOP_DECR/W0h Open-loop deceleration rate in reverse drive (% of open-loop acceleration)
  • 0h = 50%
  • 1h = 60%
  • 2h = 70%
  • 3h = 80%
  • 4h = 90%
  • 5h = 100%
  • 6h = 125%
  • 7h = 150%

8.4.2 INT_ALGO_2 Register (Offset = A2h) [Reset = 00000000h]

INT_ALGO_2 is shown in Figure 8-24 and described in Table 8-32.

Return to the Summary Table.

Register to configure internal algorithm parameters2

Figure 8-24 INT_ALGO_2 Register
3130292827262524
PARITYFLUX_WEAKENING_KP
R-0hR/W-0h
2322212019181716
FLUX_WEAKENING_KPFLUX_WEAKENING_KI
R/W-0hR/W-0h
15141312111098
FLUX_WEAKENING_KIFLUX_WEAKENING_ENCL_SLOW_ACC
R/W-0hR/W-0hR/W-0h
76543210
CL_SLOW_ACCACTIVE_BRAKE_BUS_CURRENT_SLEW_RATEEEPROM_LOCK_MODEDYNAMIC_SAMPLING_EN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-32 INT_ALGO_2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-21FLUX_WEAKENING_KPR/W0h 10-bit value for flux weakening Kp
FLUX_WEAKENING_KP is divided in 2 sections - SCALE(9:8) and VALUE(7:0)
Kp = 0.1 × VALUE / 10^SCALE.
20-11FLUX_WEAKENING_KIR/W0h 10-bit value for flux weakening Ki
FLUX_WEAKENING_KI is divided in 2 sections - SCALE(9:8) and VALUE(7:0)
Ki = 10.0 × VALUE / 10^SCALE).
10FLUX_WEAKENING_ENR/W0h Flux weakening enable
  • 0h = Disable
  • 1h = Enable
9-6CL_SLOW_ACCR/W0h Closed loop acceleration when estimator is not yet fully aligned (Applicable only if CTRL_MODE = 0h) and acceleration/deacceleration during BUS_POWER_LIMIT_ENABLE =1h or SPEED_LIMIT_ENABLE = 1h Speed control (Hz/s)
Power control (W/s)
Current control (0.1A/s)
Modulation index control(0.01% modulation index/s)
  • 0h = 0.1
  • 1h = 1
  • 2h = 2
  • 3h = 3
  • 4h = 5
  • 5h = 10
  • 6h = 20
  • 7h = 30
  • 8h = 40
  • 9h = 50
  • Ah = 100
  • Bh = 200
  • Ch = 500
  • Dh = 750
  • Eh = 1000
  • Fh = 2000
5-3ACTIVE_BRAKE_BUS_CURRENT_SLEW_RATER/W0h Active braking bus current slew rate
  • 0h = 10 A/s
  • 1h = 50 A/s
  • 2h = 100 A/s
  • 3h = 250 A/s
  • 4h = 500 A/s
  • 5h = 1000 A/s
  • 6h = 5000 A/s
  • 7h = No Limit
2-1EEPROM_LOCK_MODER/W0h EEPROM access lock mode
  • 0h = EEPROM read and write allowed without a valid EEPROM_LOCK_KEY
  • 1h = EEPROM read and write allowed with a valid EEPROM_LOCK_KEY
  • 2h = EEPROM read allowed with a valid EEPROM_LOCK_KEY, write is locked permanently
  • 3h = EEPROM read and write is locked permanently
0DYNAMIC_SAMPLING_ENR/W0h Dynamic sampling enable
  • 0h = Dynamic sampling is disabled
  • 1h = Dynamic sampling is enabled