SLLSFZ8 November   2025 MCF8329HS-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  Low-Side Current Sense Amplifier
      5. 7.3.5  Device Interface Modes
        1. 7.3.5.1 Interface - Control and Monitoring
        2. 7.3.5.2 I2C Interface
      6. 7.3.6  Motor Control Input Options
        1. 7.3.6.1 Analog-Mode Motor Control
        2. 7.3.6.2 PWM-Mode Motor Control
        3. 7.3.6.3 Frequency-Mode Motor Control
        4. 7.3.6.4 I2C based Motor Control
        5. 7.3.6.5 Input Control Signal Profiles
          1. 7.3.6.5.1 Linear Control Profiles
          2. 7.3.6.5.2 Staircase Control Profiles
          3. 7.3.6.5.3 Forward-Reverse Profiles
          4. 7.3.6.5.4 Multi-Reference Mode Operation
          5. 7.3.6.5.5 Input Reference Transfer Function without Profiler
      7. 7.3.7  Bootstrap Capacitor Initial Charging
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
          1. 7.3.9.3.1 Reverse Drive Tuning
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open Loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 Closed loop accelerate
        2. 7.3.10.2 Speed PI Control
        3. 7.3.10.3 Current PI Control
        4. 7.3.10.4 Overmodulation
        5. 7.3.10.5 Power Loop
        6. 7.3.10.6 Modulation Index Control
        7. 7.3.10.7 Motor Speed Limit
        8. 7.3.10.8 Input DC Power Limit
      11. 7.3.11 Maximum Torque Per Ampere (MTPA) Control
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Single Hall Sensor Operation
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Active Braking
      18. 7.3.18 Output PWM Switching Frequency
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behavior During Fault
      23. 7.3.23 Protections
        1. 7.3.23.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.23.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.23.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.23.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.23.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.23.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.23.7  Thermal Shutdown (OTSD)
        8. 7.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE = 111b)
        9. 7.3.23.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.23.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 111b)
        10. 7.3.23.10 Motor Lock (MTR_LCK)
          1. 7.3.23.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xb or 010b)
          2. 7.3.23.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE = 011b or 10xb)
          3. 7.3.23.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 110b)
          4. 7.3.23.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 111b)
        11. 7.3.23.11 Motor Lock Detection
          1. 7.3.23.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.23.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.23.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.23.12 MPET Faults
        13. 7.3.23.13 IPD Faults
        14. 7.3.23.14 Dry Run Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 Oscillator Source
      3. 7.5.3 External Watchdog with MCU Reset
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Algorithm_Control Registers
    4. 9.4 Device_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Typical Applications
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3.      Gate Drive Current
      4.      Gate Resistor Selection
      5.      System Considerations in High Power Designs
      6.      Capacitor Voltage Ratings
      7.      External Power Stage Components
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Bulk Capacitance
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Thermal Considerations
        1. 10.4.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

9.1 Fault_Status Registers

Table 9-1 lists the memory-mapped registers for the Fault_Status registers. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified.

Table 9-1 FAULT_STATUS Registers
OffsetAcronymRegister NameSection
0hGATE_DRIVER_FAULT_STATUSFault Status RegisterSection 9.1.1
2hCONTROLLER_FAULT_STATUSFault Status RegisterSection 9.1.2
24ChEEPROM_FAULT_STATUSEEPROM Fault Status RegisterSection 9.1.3

Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section.

Table 9-2 Fault_Status Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

9.1.1 GATE_DRIVER_FAULT_STATUS Register (Offset = 0h) [Reset = 00000000h]

GATE_DRIVER_FAULT_STATUS is shown in Figure 9-1 and described in Table 9-3.

Return to the Summary Table.

Status of various gate driver faults

Figure 9-1 GATE_DRIVER_FAULT_STATUS Register
3130292827262524
DRIVER_FAULTRESERVEDOTS_FAULTOCP_VDS_FAULTOCP_SNS_FAULTBST_UV_FAULTGVDD_UV_FLTDRV_OFF
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDVDS_LC_FAULTVDS_LB_FAULTVDS_LA_FAULTRESERVEDVDS_HC_FAULTVDS_HB_FAULTVDS_HA_FAULT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-3 GATE_DRIVER_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31DRIVER_FAULTR0h Indicates the logical OR of driver fault registers
  • 0h = No Gate Driver fault condition is detected
  • 1h = Gate Driver fault condition is detected
30RESERVEDR0h Reserved
29OTS_FAULTR0h Overtemperature fault
  • 0h = No overtemperature warning / shutdown is detected
  • 1h = Overtemperature warning / shutdown is detected
28OCP_VDS_FAULTR0h Overcurrent VDS fault status
  • 0h = No VDS fault condition is detected
  • 1h = VDS fault condition is detected
27OCP_SNS_FAULTR0h Overcurrent sense fault status
  • 0h = No overcurrent sense fault condition is detected
  • 1h = Overcurrent sense fault condition is detected
26BST_UV_FAULTR0h Bootstrap undervoltage protection status
  • 0h = No BST undervoltage fault condition is detected
  • 1h = BST undervoltage fault condition is detected
25GVDD_UV_FLTR0h GVDD undervoltage fault status
  • 0h = No GVDD undervoltage fault condition is detected
  • 1h = GVDD undervoltage fault condition is detected
24DRV_OFFR0h DRV off status
  • 0h = DRV is ON
  • 1h = DRVOff state detected
23-7RESERVEDR0h Reserved
6VDS_LC_FAULTR0h VDS fault status on low-side switch of OUTC
  • 0h = No VDS fault detected on low-side switch of OUTC
  • 1h = VDS fault detected on low-side switch of OUTC
5VDS_LB_FAULTR0h VDS fault status on low-side switch of OUTB
  • 0h = No VDS fault detected on low-side switch of OUTB
  • 1h = VDS fault detected on low-side switch of OUTB
4VDS_LA_FAULTR0h VDS fault status on low-side switch of OUTA
  • 0h = No VDS fault detected on low-side switch of OUTA
  • 1h = VDS fault detected on low-side switch of OUTA
3RESERVEDR0h Reserved
2VDS_HC_FAULTR0h VDS fault status on high-side switch of OUTC
  • 0h = No VDS fault detected on high-side switch of OUTC
  • 1h = VDS fault detected on high-side switch of OUTC
1VDS_HB_FAULTR0h VDS fault status on high-side switch of OUTB
  • 0h = No VDS fault detected on high-side switch of OUTB
  • 1h = VDS fault detected on high-side switch of OUTB
0VDS_HA_FAULTR0h VDS fault status on high-side switch of OUTA
  • 0h = No VDS fault detected on high-side switch of OUTA
  • 1h = VDS fault detected on high-side switch of OUTA

9.1.2 CONTROLLER_FAULT_STATUS Register (Offset = 2h) [Reset = 00000000h]

CONTROLLER_FAULT_STATUS is shown in Figure 9-2 and described in Table 9-4.

Return to the Summary Table.

Status of various controller faults

Figure 9-2 CONTROLLER_FAULT_STATUS Register
3130292827262524
CONTROLLER_FAULTRESERVEDRESERVEDRESERVEDNO_MTR_PHASE_CNO_MTR_PHASE_BNO_MTR_PHASE_AMPET_BEMF_FAULT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
ABN_SPEEDABN_BEMFNO_MTRMTR_LCKLOCK_LIMITHW_LOCK_LIMITDCBUS_UNDER_VOLTAGEDCBUS_OVER_VOLTAGE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
SPEED_LOOP_SATURATIONCURRENT_LOOP_SATURATIONMAX_SPEED_SATURATIONBUS_POWER_LIMIT_SATURATIONEEPROM_WRITE_LOCK_SETEEPROM_READ_LOCK_SETDRY_RUN_DETECTION_STATUSRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDI2C_CRC_FAULT_STATUSEEPROM_ERR_STATUSRESERVEDWATCHDOG_FAULTRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-4 CONTROLLER_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31CONTROLLER_FAULTR0h Indicates the logical OR of controller fault status registers
30RESERVEDR0h Reserved
29RESERVEDR0h Reserved
28RESERVEDR0h Reserved
27NO_MTR_PHASE_CR0h Indicates loss of Phase C causes no motor fault
26NO_MTR_PHASE_BR0h Indicates loss of Phase B causes no motor fault
25NO_MTR_PHASE_AR0h Indicates loss of Phase A causes no motor fault
24MPET_BEMF_FAULTR0h Indicates an error during BEMF constant measurement
23ABN_SPEEDR0h Indicates abnormal speed motor lock condition
22ABN_BEMFR0h Indicates abnormal BEMF motor lock condition
21NO_MTRR0h Indicates no motor (loss of phase) fault
20MTR_LCKR0h Indicates when one of the motor lock (abnormal BEMF/speed, no motor) is triggered
19LOCK_LIMITR0h Indicates Lock Ilimit fault
18HW_LOCK_LIMITR0h Indicates Hardware lock Ilimit fault
17DCBUS_UNDER_VOLTAGER0h Indicates configurable under voltage fault on PVDD
16DCBUS_OVER_VOLTAGER0h Indicates configurable over voltage fault on PVDD
15SPEED_LOOP_SATURATIONR0h Indicates speed loop saturation
14CURRENT_LOOP_SATURATIONR0h Indicates current loop saturation
13MAX_SPEED_SATURATIONR0h Indicates maximum speed limit saturation
12BUS_POWER_LIMIT_SATURATIONR0h Indicates maximum (input DC bus) power limit saturation
11EEPROM_WRITE_LOCK_SETR0h Indicates EEPROM write lock is set
10EEPROM_READ_LOCK_SETR0h Indicates EEPROM read lock is set
9DRY_RUN_DETECTION_STATUSR0h Indicates dry run detection
8-7RESERVEDR0h Reserved
6I2C_CRC_FAULT_STATUSR0h Indicates CRC fault in I2C packet
5EEPROM_ERR_STATUSR0h Indicates error in EEPROM
4RESERVEDR0h Reserved
3WATCHDOG_FAULTR0h indicates Watchdog fault
2RESERVEDR0h Reserved
1RESERVEDR0h Reserved
0RESERVEDR0h Reserved

9.1.3 EEPROM_FAULT_STATUS Register (Offset = 24Ch) [Reset = 0000h]

EEPROM_FAULT_STATUS is shown in Figure 9-3 and described in Table 9-5.

Return to the Summary Table.

EEPROM Fault Status Register

Figure 9-3 EEPROM_FAULT_STATUS Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDEEPROM_CRC_FLT_STSRESERVEDEEPROM_PARITY_FLT_STSRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
Table 9-5 EEPROM_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0h Reserved
4EEPROM_CRC_FLT_STSR0h EEPROM CRC error fault status
  • 0h = EEPROM CRC Error fault condition is not detected
  • 1h = EEPROM CRC Error fault condition is detected
3RESERVEDR0h Reserved
2EEPROM_PARITY_FLT_STSR0h EEPROM parity error fault status
  • 0h = EEPROM Parity error fault condition is not detected
  • 1h = EEPROM Parity error fault condition is detected
1RESERVEDR0h Reserved
0RESERVEDR0h Reserved