SLUUAQ3A April 2016 – October 2022 BQ4050
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Settings | Configuration | SOC Flag Config B | H1 | 0x00 | 0xFF | 0x8C | Hex |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FCCLEAR RSOC | FCSETRSOC | FCCLEARV | FCSETV | FDCLEAR RSOC | FDSETRSOC | FDCLEARV | FDSETV |
| FCCLEARRSOC (Bit 7): Enable FC flag clear by RSOC threshold | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |
| FCSETRSOC (Bit 6): Enable FC flag set by RSOC threshold | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| FCCLEARV (Bit 5): Enable FC flag clear by cell voltage threshold | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| FCSETV (Bit 4): Enable FC flag set by cell voltage threshold | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| FDCLEARRSOC (Bit 3): Enable FD flag clear by RSOC threshold | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |
| FDSETRSOC Bit 2: Enable FD flag set by RSOC threshold | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |
| FDCLEARV (Bit 1): Enable FD flag clear by cell voltage threshold | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| FDSETV (Bit 0): Enable FD flag set by cell voltage threshold | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |