SLUUAQ3A April 2016 – October 2022 BQ4050
This command returns the SafetyAlert() flags on ManufacturerBlockAccess() or ManufacturerData().
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | RSVD | RSVD | RSVD | UTD | UTC | PCH GC | CHGV | CHGC | OC | CTOS | CTO | PTOS | PTO | RSVD | OTF |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | CUVC | OTD | OTC | ASC DL | RSVD | ASC CL | RSVD | AOL DL | RSVD | OCD2 | OCD1 | OCC2 | OCC1 | COV | CUV |
| RSVD (Bits 31–28): Reserved. Do not use. | ||
| UTD (Bit 27): Undertemperature During Discharge | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| UTC (Bit 26): Undertemperature During Charge | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| PCHGC (Bit 25): Over-Precharge Current | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| CHGV (Bit 24): Overcharging Voltage | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| CHGC (Bit 23): Overcharging Current | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| OC (Bit 22): Overcharge | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| CTOS (Bit 21): Charge Timeout Suspend | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| CTO (Bit 20): Charge Timeout | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| PTOS (Bit 19): Precharge Timeout Suspend | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| PTO (Bit 18): Precharge Timeout | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| RSVD (Bit 17): Reserved. Do not use. | ||
| OTF (Bit 16): Overtemperature FET | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| RSVD (Bit 15): Reserved. Do not use. | ||
| CUVC (Bit 14): Cell Undervoltage Compensated | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| OTD (Bit 13): Overtemperature During Discharge | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| OTC (Bit 12): Overtemperature During Charge | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| ASCDL (Bit 11): Short-Circuit During Discharge Latch | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| RSVD (Bit 10): Reserved. Do not use. | ||
| ASCCL (Bit 9): Short-Circuit During Charge Latch | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| RSVD (Bit 8): Reserved. Do not use. | ||
| AOLDL (Bit 7): Overload During Discharge Latch | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| RSVD (Bit 6): Reserved. Do not use. | ||
| OCD2 (Bit 5): Overcurrent During Discharge 2 | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| OCD1 (Bit 4): Overcurrent During Discharge 1 | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| OCC2 (Bit 3): Overcurrent During Charge 2 | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| OCC1 (Bit 2): Overcurrent During Charge 1 | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| COV (Bit 1): Cell Overvoltage | ||
| 1 = | Detected | |
| 0 = | Not Detected | |
| CUV (Bit 0): Cell Undervoltage | ||
| 1 = | Detected | |
| 0 = | Not Detected | |