SLVAE87A December   2020  – October 2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 NPN LDO Supply
  5. 2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM
    1. 2.1 Base Device
    2. 2.2 Design Summary
  6. 3 OTP Programming
  7. 4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
    1. 4.1 Cell Voltage Sense (VCn)
    2. 4.2 Cell Balancing (CBn)
      1. 4.2.1 Non-Adjacent Cell Balancing
      2. 4.2.2 Adjacent Cell Balancing
      3. 4.2.3 Cell Balancing With External FET
    3. 4.3 Using Fewer Than 16 Cells
      1. 4.3.1 Design Summary
  8. 5 Bus Bar Support
    1. 5.1 Bus Bar on BBP/BBN
    2. 5.2 Typical Connection
      1. 5.2.1 Cell Balancing Handling
    3. 5.3 Bus Bar on Individual VC Channel
    4. 5.4 Multiple Bus Bar Connections
      1. 5.4.1 Two Bus Bar Connections to One Device
      2. 5.4.2 Three Bus Bar Connections to One Device
      3. 5.4.3 Cell Balancing Handling
  9. 6 TSREF
  10. 7 General Purpose Input-Output (GPIO) Configurations
    1. 7.1 Ratiometric Temperature Measurement
    2. 7.2 SPI Mode
      1. 7.2.1 Support 8 NTC Thermistors With SPI Slave Device
      2. 7.2.2 Design Summary
  11. 8 Base and Bridge Device Configuration
    1. 8.1 Power Mode Pings and Tones
      1. 8.1.1 Power Mode Pings
      2. 8.1.2 Power Mode Tones
      3. 8.1.3 Ping and Tone Propagation
    2. 8.2 UART Physical Layer
      1. 8.2.1 Design Considerations
  12. 9 Daisy-Chain Stack Configuration
    1. 9.1 Communication Line Isolation
      1. 9.1.1 Capacitor Only Isolation
      2. 9.1.2 Capacitor and Choke Isolation
      3. 9.1.3 Transformer Isolation
      4. 9.1.4 Design Summary
    2. 9.2 Ring Communication
    3. 9.3 Re-Clocking
      1. 9.3.1 Design Summary
  13. 10Multi-Drop Configuration
  14. 11Main ADC Digital LPF
  15. 12AUX Anti Aliasing Filter (AAF)
  16. 13Layout Guidelines
    1. 13.1 Ground Planes
    2. 13.2 Bypass Capacitors for Power Supplies and References
    3. 13.3 Cell Voltage Sensing
    4. 13.4 Daisy Chain Communication
  17. 14BCI Performance
  18. 15Common and Differential Mode Noise
    1. 15.1 Design Consideration
  19. 16Revision History

3 OTP Programming

There are memory locations that are programmable in non-volatile memory (NVM) using OTP (One Time Progammable). The memory space is divided in two groups: factory space and customer space. The factory space stores the device configurations that are essential for normal operation. This space is not accessible by the host. The customer space contains the default device settings that the host system can customize for their application configuration. This space is readable and programmable by the host.

Follow the procedures found below for OTP programming:

  1. Unlock the OTP programming.
    1. Write the following data to OTP_PROG_UNLOCK1A to OTP_PROG_UNLOCK1D:
      1. OTP_PROG_UNLOCK1A <- data 0x02
      2. OTP_PROG_UNLOCK1B <- data 0xB7
      3. OTP_PROG_UNLOCK1C <- data 0x78
      4. OTP_PROG_UNLOCK1D <- data 0xBC
    2. Do another write with following data to OTP_PROG_UNLOCK2A to OTP_PROG_UNLOCK2D registers.
      1. OTP_PROG_UNLOCK2A <- data 0x7E
      2. OTP_PROG_UNLOCK2B <- data 0x12
      3. OTP_PROG_UNLOCK2C <- data 0x08
      4. OTP_PROG_UNLOCK2D <- data 0x6F
    Note: Each block of registers must be written in order (that is A,B,C, then D) with no other writes or reads between. The best practice is to use the same Write command to update. If there is any attempt to update the registers out of sequence or if another register is written/read between writes, the entire sequence must be redone.
  2. Check to confirm the OTP unlock procedure is successful.
    1. Read to confirm OTP_PROG_STAT[UNLOCK] = 1.
    Note: Issuing a Read command after step 1 is allowed, but issuing a [PROG_GO] must be the next write command after the unlock procedures.
  3. Select the proper OTP page and start the OTP programing.
    1. To program page1, set OTP_PROG_CTRL[PAGESEL][PROG_GO] = 0x01, OR
    2. To program page2, set OTP_PROG_CTRL[PAGESEL][PROG_GO] = 0x03.
  4. Wait tPROG for the OTP programming to complete.
  5. Check to ensure there is no error during OTP programming. The following bits are expected to be ‘1’ after a successful OTP programming.
    1. OTP_PROG_STAT[DONE] = 1, OTP programming is done. No other bit shall be set in this register.
    2. If page 1 is programmed, OTP_CUST*_STAT*[PROGOK], [TRY], [OVOK] and [UVOK] bits shall be ‘1’. Other bits shall be ‘0’.
    3. If page 2 is programmed, OTP_CUST1_STAT[LOADED], [PROGOK], [TRY], [OVOK], and [UVOK] bits shall be ‘1’. Other bits in OTP_CUST*_STAT shall be '0'.
  6. Issue a digital reset to reload the registers with the updated OTP values.
    1. CONTROL1[SOFT_RESET] = 1

During the programming procedure, the device performs a programming voltage stability test prior to actually programming the OTP. If a programming voltage fails the stability test, the device does not set the OTP_CUST*_STAT[TRY] bit, giving the customer another attempt to program the page again.

If the host incorrectly selected a page for programming, the OTP_PROG_STAT[PROGERR] bit is set. This indicates that the selected page is not available to be programmed. Select the correct page and retry programming.