SNOSDM1 December   2025 TLV6722

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Separate Power Supplies (H_VCC, M_VCC)
      2. 8.4.2 Low Supply Reset Deassertion
      3. 8.4.3 Power-On Reset (POR)
      4. 8.4.4 Inputs (INT/RSTn, LPWn/PRSn(/ePPS), M_INT)
      5. 8.4.5 Outputs (M_RSTn, M_LPWn, M_CLK)
      6. 8.4.6 Switching Thresholds and Hysteresis
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 TLV6722 YBJ Package, 9-pin DSBGA (Top View)
Figure 5-2 TLV6723, TLV6724 YBJ Package, 9-pin DSBGA (Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
TLV6722TLV6723, TLV6724
H_VCCA1A1PHost-side VCC, connect to host-side 3.3V on plug-in to connect R2 in the OSFP/OSFP-XD INT/RSTn circuit. Powers internal comparators, reference, and clock buffer (TLV6723 and TLV6724).
INT/RSTnB1B1I/OMulti-level bi-directional pin, connect to host-side INT/RSTn on plug-in to set voltage levels for OSFP/OSFP-XD INT/RSTn circuit.
LPWn/PRSn/ePPS-C1I/OMulti-level bi-directional pin, connect to host-side LPWn/PRSn/ePPS on plug-in to set voltage levels for OSFP-XD LPWn/PRSn/ePPS circuit and for superimposed ePPS/reference clock input.
LPWn/PRSn C1 - I/O Multi-level bi-directional pin, connect to host-side LPWn/PRSn on plug-in to set voltage levels for OSFP/OSFP-XD LPWn/PRSn circuit.
M_VCCA2A2PModule-side VCC, sets interrupt input, M_LPWn comparator output, and clock buffer output logic levels. Short to H_VCC for 3.3V logic.
GNDB2B2GGround
M_CLK-C2OClock buffer output, used for OSFP-XD ePPS/reference clock support.
NCC2--No connect, leave floating.
M_INTA3A3IModule interrupt input, signal from module to raise an interrupt to the host. Digital input that controls R3 connection to ground.
M_RSTnB3B3OModule reset output (open-drain), signal from host to module to reset module.
M_LPWnC3C3OModule low power mode output (push-pull), signal from host to module to put module in low power mode.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.