SNOSDM1 December   2025 TLV6722

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Separate Power Supplies (H_VCC, M_VCC)
      2. 8.4.2 Low Supply Reset Deassertion
      3. 8.4.3 Power-On Reset (POR)
      4. 8.4.4 Inputs (INT/RSTn, LPWn/PRSn(/ePPS), M_INT)
      5. 8.4.5 Outputs (M_RSTn, M_LPWn, M_CLK)
      6. 8.4.6 Switching Thresholds and Hysteresis
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Overview

The TLV672x are a family of devices that fully integrates the module-side INT/RSTn and LPWn/PRSn(/ePPS) circuits as defined by the OSFP and OSFP-XD MSAs. The TLV672x are available in the small-size 1.2mm x 1.2mm DSBGA-9 package that is well-suited for space-critical OSFP and OSFP-XD module designs. Internal to the device are factory-trimmed passives (R2, R3, R13, and R15) to set the voltage zones for the INT/RSTn and LPWn/PRSn(/ePPS) circuits. Two integrated comparators and a reference handle the host-to-module M_RSTn and M_LPWn signals. An integrated open-drain buffer connects and disconnects R3 to allow for module-to-host interrupt signaling. The TLV672x family is differentiated based on the availability and the configuration of the integrated clock buffer for ePPS/reference clock support. TLV6722 is a device without an integrated clock buffer. TLV6723 is a device with an integrated clock buffer with self-shutdown functionality. TLV6724 is a device with an integrated always-on clock buffer.