SNOSDM1 December 2025 TLV6722
PRODUCTION DATA
M_RSTn is the hardware reset signal for the OSFP/OSFP-XD module system. The assertion of M_RSTn holds the module state machine in the reset steady state, so it's advantageous to know at what H_VCC voltage M_RSTn gets deasserted to make sure that downstream electronics properly wake-up. M_RSTn deassertion depends on many characteristics of the TLV672x such as H_VCC, VIT+, R2, and R3. To account for all of the factors that determine M_RSTn deassertion, the VWAKE_UP specification is provided as a value of H_VCC that results in a M_RSTn deassertion. This specification is a system-level specification that is measured with the host-side R1 (68kΩ resistor) to account for host-side contributions to INT/RSTn.
The above figure shows the M_RSTn output with a pull-up resistor to H_VCC while H_VCC ramps. In Region 1, H_VCC is below VPOR and active circuitry within the TLV672x is off, which results in the output being Hi-Z. In Region 2, H_VCC is above VPOR and there is now enough voltage headroom for internal circuitry to operate. However, INT/RSTn still remains below VIT+ due to the low H_VCC and the INT/RSTn resistive divider, so the M_RSTn is output low (reset asserted). In Region 3, H_VCC is high enough such that INT/RSTn exceeds VIT+, so the M_RSTn transitions to Hi-Z (reset deasserted).VWAKE_UP is the boundary at which M_RSTn gets deasserted for the OSFP module system to transition out of the reset steady state.