SNOSDM1 December   2025 TLV6722

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Separate Power Supplies (H_VCC, M_VCC)
      2. 8.4.2 Low Supply Reset Deassertion
      3. 8.4.3 Power-On Reset (POR)
      4. 8.4.4 Inputs (INT/RSTn, LPWn/PRSn(/ePPS), M_INT)
      5. 8.4.5 Outputs (M_RSTn, M_LPWn, M_CLK)
      6. 8.4.6 Switching Thresholds and Hysteresis
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4.1 Separate Power Supplies (H_VCC, M_VCC)

The TLV672x has separate host-side and module-side power supplies (H_VCC, M_VCC) to allow for module-side voltage level compatibility without external level shifting. This allows for input voltage zones to be compliant with the OSFP and OSFP-XD MSAs while directly driving lower voltage MCU.

The H_VCC pin supplies power to the device and determines the input voltage zones for the INT/RSTn circuit. The M_VCC pin supplies power to the M_LPWn comparator output stage, clock buffer output stage (TLV6723 and TLV6724), and open-drain M_INT buffer input stage. M_VCC defines the logic levels for M_LPWn, M_CLK, and M_INT.

H_VCC can range from a minimum of 3.135V and up to a maximum of 3.465V to establish the proper voltage zones compliant with the OSFP and OSFP-XD MSAs. The active devices internal to the TLV672x family remains functional with H_VCC from 3V and up to 3.6V, but the INT/RSTn voltage zones set by H_VCC are no longer be compliant with OSFP and OSFP-XD MSAs if H_VCC goes beyond the 3.135V to 3.465V range.

M_VCC can range from a minimum of 1.1V and up to a maximum of H_VCC. This allows the module-side input and outputs to be powered by LVCMOS voltages like 2.5V, 1.8V, 1.5V, and 1.2V.