SNOSDM1 December   2025 TLV6722

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Separate Power Supplies (H_VCC, M_VCC)
      2. 8.4.2 Low Supply Reset Deassertion
      3. 8.4.3 Power-On Reset (POR)
      4. 8.4.4 Inputs (INT/RSTn, LPWn/PRSn(/ePPS), M_INT)
      5. 8.4.5 Outputs (M_RSTn, M_LPWn, M_CLK)
      6. 8.4.6 Switching Thresholds and Hysteresis
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4.3 Power-On Reset (POR)

The TLV672x devices have an internal Power-On Reset (POR) circuit for known start-up or power-down conditions. While power supplies are ramping up, the POR circuitry is activated for up to 500μs after the VPOR threshold of 1.5V is crossed.

The TLV672x devices have the following POR behavior during the POR period (tON):

  • M_RSTn is held Hi-Z
  • M_LPWn is held LOW
  • M_CLK is held LOW (TLV6723 and TLV6724)

The TLV672x POR circuitry monitors the voltage at the H_VCC pin. When H_VCC is greater than VPOR, then after a delay period (tON), M_RSTn, M_LPWn, and M_CLK reflect input conditions.

There is no delay on power down. M_RSTn, M_LPWn, and M_CLK enters the POR state immediately when H_VCC falls below VPOR.