SNVSCO1 November   2025 LM5126A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin )
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP, CSN)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP, CSN)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 3 Phase Operation
      3. 7.1.3 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 AC Loop Response Curve
        5. 7.2.3.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB-pin)

The device integrates N-channel logic MOSFET drivers. The LO driver is powered by VCC and the HO driver is powered by HB. When the SW-pin voltage is approximately 0V by turning on the low-side MOSFET, the capacitor CHB is charged from VCC through the internal boot diode. The recommended value of CHB is 0.1μF. During shutdown, the gate drivers outputs are high impedance.

The LO and HO output is controlled with an adaptive dead-time methodology, which makes sure that both outputs are not turned on at the same time to prevent shoot through. When the device turns on LO the adaptive dead-time logic turns off HO and waits for the HO − SW voltage to drop below typically 1.5V, then LO is turned on after a small programmable dead-time delay tDHL. Also the HO driver turn-on is delayed until the LO - PGND voltage has discharged below typically 1.5V. HO is then turned on after the same programmable dead-time delay tDLH.

If the driver output voltage is lower than the MOSFET gate plateau voltage during start-up, the converter cannot start up properly and can be stuck at the maximum duty cycle in a high-power dissipation state. Avoid this condition by selecting a lower threshold MOSFET or by turning on the device when the BIAS-pin voltage is sufficient. During bypass operation the minimum HO − SW voltage is 3.75V.

The hiccup mode fault protection is triggered by VHB-UVLO. If the HB − SW voltage is less than the HB UVLO threshold (VHB-UVLO), LO turns on by force for 75ns to replenish the boost capacitor. The device allows up to four consecutive replenish switching cycles. After the maximum four consecutive boot replenish switching cycles, the device skips switching for 12 cycles. If the device fails to replenish the boost capacitor after the four sets of the four consecutive replenish switching cycles, the device stops switching and enters 512 cycles of hiccup mode off-time. During the hiccup mode off-time PGOOD = low and the SS-pin is grounded.

If required adjust the slew rate of the switching node voltage by adding a gate resistor in parallel with pull-down PNP transistor. The resistor decreases the effective dead-time.

LM5126A-Q1 Slew Rate Control Figure 6-23 Slew Rate Control