SNVSCO1 November   2025 LM5126A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin )
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP, CSN)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP, CSN)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 3 Phase Operation
      3. 7.1.3 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 AC Loop Response Curve
        5. 7.2.3.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.10 Vout Programming

For fixed output voltage, program VOUT by connecting a resistor to ATRK/DTRK and turn on precise internal 20μA current source.

Equation 51. R A T R K = V o u t _ m a x 6 V × 10 k Ω = 75 k Ω

For class-H audio application, adjust Vout to optimize the efficiency. Apply analog tracking or digital tracking with ATRK/DTRK.

Program the output voltage by digital PWM signal (DTRK). The duty cycle DTRK is found as:

Equation 52. DTRK_max=Vout_max75V=60%
Equation 53. DTRK_min=Vout_min75V=10.7%

Make sure the DTRK frequency is between 100kHz and 2200kHz. The DTRK PWM signal must be applied when the IC is enabled.

For analog tracking, apply a voltage to ATRK/DTRK to program Vout. The voltage is found as:

Equation 54. V A T R K _ m a x = V o u t _ m a x 30 = 1.5 V
Equation 55. V A T R K _ m i n = V o u t _ m i n 30 = 0.267 V

Use a two stage RC filter with offset to convert a digital PWM signal to analog voltage as shown in Figure 7-8.

LM5126A-Q1 Two Stage RC Filter to ATRK/DTRK Figure 7-8 Two Stage RC Filter to ATRK/DTRK

The two stage RC filter is used to filter the PWM signal into a smooth analog voltage. The two stage RC filter is selected considering voltage ripple and settling time on ATRK/DTRK.

100% PWM duty cycle sets the output voltage to Vout_max and 0% PWM duty cycle sets the output voltage to Vout_min. Rt and Rb are used to adjust ATRK/DTRK offset voltage.

The Vtrk_max and Vtrk_min can be found as,

Equation 56. VATRK_max=VddRb2Rf+RaRt+Rb
Equation 57. VATRK_min=Vdd2Rf+RaRb2Rf+RaRb+Rt

Where Vdd is the amplitude of the PWM signal; d is the PWM duty cycle.

The AC transfer function from input to VATRK can be found as,

Equation 58. Gtrks=RL2Rf+RL1+2ζsωn+sωn2

Where

Equation 59. RL=Ra+RbRt
Equation 60. ωn=1Rf×CfRL2Rf+RL
Equation 61. ζ=12RfRL+3RL2Rf+RL

The roots of the denominator can be found as,

Equation 62. s1=-ζωn+ωnζ2-1
Equation 63. s2=-ζωn-ωnζ2-1

As ζ>1, this is an overdamped second order system. s1 is the dominate pole. 2% settling time ts can be estimated as,

Equation 64. ts=1s1⋅ln-0.02⋅2s1ζ2-1ωn

In this application, 400kHz PWM frequency is used. Rf=4.99kΩ, Cf=47nF, Ra=1.5kΩ, Rt=51kΩ, Rb=7.87kΩ are selected. The 2% settling time is around 1.3ms.