SNVSCO1 November   2025 LM5126A-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin )
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP, CSN)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP, CSN)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 3 Phase Operation
      3. 7.1.3 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 AC Loop Response Curve
        5. 7.2.3.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Inductor Selection Lm

Three main parameters are considered when selecting the inductance value: Inductor current ripple ratio (RR), falling slope of the inductor current and the RHPZ frequency of the control loop.

  • The inductor current ripple ratio is selected to balance the winding loss and core loss of the inductor. As the ripple current increases the core loss increases and the copper loss decreases.
  • It is necessary for the falling slope of the inductor current to be small enough to prevent sub-harmonic oscillation. A larger inductance value results in a smaller falling slope of the inductor current.
  • Place the RHPZ at high frequency to allow a higher crossover frequency of the control loop. As the inductance value decreases the RHPZ frequency increases.

According to peak current mode control theory, it is necessary that the slope compensation ramp is greater than half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle, that is:

Equation 32. Vslope×fsw>Vout_max-Vin_min2×Lm×Rcs

where

  • Vslope is a 48mV peak (at 100% duty cycle) slope compensation ramp at the input of the current sense amplifier.

The lower limit of the inductance is found as,

Equation 33. Lm>Vout_max-Vin_min2×Vslope×fsw×Rcs

Rcs is estimated to be 1.5mΩ, so the following is found,

Equation 34. Lm>1.4µH

The RHPZ frequency is found as,

Equation 35. ωRHPZ=Rout×D'2Lm_eq

It is necessary that the crossover frequency is lower than 1/5 of RHPZ frequency,

Equation 36. fc<15×ωRHPZ2π

Assume a crossover frequency of 1kHz is desired, the upper limit of the inductance is found as,

Equation 37. Lm<5.2µH

The inductor ripple current is typically set between 30% and 70% of the full load current, known as a good compromise between core loss and winding loss of the inductor.

Per phase input current is calculated as,

Equation 38. I i n _ v i n m a x = P o u t η × V i n _ m a x = 29.2 A

In continuous conduction mode (CCM) operation, the maximum ripple ratio occurs at a duty cycle of 33%. The input voltage that result in a maximum ripple ratio is found as,

Equation 39. Vin_RRmax=Vout_max×1-0.33=30V

Thus, it is necessary to use the maximum input voltage Vin_max to calculate the maximum ripple ratio.

For this example, a ripple ratio of 0.3, 30% of the input current was chosen. Knowing the switching frequency and the typical output voltage, the inductor value is calculated as follows,

Equation 40. Lm=Vin_maxIin×RR×1fsw×1-Vin_maxVout_max=18V29.2A×0.3×1400kHz×0.6=3.1µH

The closest standard value of 3.3μH was chosen for Lm.

The inductor ripple current at typical input voltage is calculated as:

Equation 41. Ipp=Vin_typLm×1fsw×1-Vin_typVout=7.4A

If a ferrite core inductor is selected, make sure the inductor does not saturate at peak current limit. The inductance of a ferrite core inductor is almost constant until saturation. Ferrite core has low core loss with a big size.

For powder core inductor, the inductance decreases slowly with increased DC current. This action leads to higher ripple current at high inductor current. For this example, the inductance drops to 70% at peak current limit compared to 0A. The current ripple at peak current limit is found as,

Equation 42. I p p _ b i a s = V i n _ t y p 0.7 × L m × 1 f s w × 1 - V i n _ t y p V o u t = 10.6 A