SNVSCO1 November   2025 LM5126A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin )
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP, CSN)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP, CSN)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 3 Phase Operation
      3. 7.1.3 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 AC Loop Response Curve
        5. 7.2.3.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.6 Operation Modes (BYPASS, DEM, FPWM)

The device supports bypass mode, forced PWM (FPWM) and diode emulation mode (DEM) operation. The mode can be changed on the fly and is set by the MODE-pin. Bypass mode is automatically activated for VOUT < VI. The device operation mode is set to DEM for VMODE < 0.4V and to FPWM for VMODE > 1.2V.

Table 6-6 Mode-Pin Settings
Operation Mode MODE-pin
DEM VMODE < 0.4V
FPWM VMODE > 1.2V

In Diode Emulation Mode (DEM) current flow from VOUT to VI is prevented. The SW-pin voltage is monitored during the high-side on time and the high-side switch is turned off when the voltage falls below the zero current detection threshold VZCD. The device works in Discontinuous Conduction Mode (DCM) for light load and finally skips pulses, which improves light load efficiency. In DEM operation when COMP falls below typically 460mV the controller starts skipping pulses. Calculate the skip entry point for the input current with formula Equation 5 and for the output current with formula Equation 6.

Equation 5. II_skip=1.5μ×VIL0.48×fSW40K+250μ×RSNS×VIL
Equation 6. IOUT_skip=VIVOUT×VIL×1.5μ0.48×fSW40K+250μ×RSNS×VIL

In Forced Pulse With Modulation Mode (FPWM) the converter keeps switching also for light load with fixed frequency in continuous conduction mode (CCM). This mode improves light load transient response.

LM5126A-Q1 Inductor current waveform for the different operation modes. Figure 6-8 Inductor current waveform for the different operation modes.

In Bypass Mode (BYPASS) VI is connected to VOUT (no regulation) by turning on the high side FET. Positive current flowing from VI to VOUT cannot be controlled while current flow from VOUT to VI is prevented for DEM setting and limited to VNCLTH for FPWM setting. An integrated charge pump provides a voltage of minimum 3.75V at HO − SW and drives 55uA (ICP). In case a MOSFET gate pull-down resistor is used make sure the charge pump can drive the leakage current of the MOSFET and the pull-down resistor. The device starts switching in case the charge pump is overloaded to keep a minimum of VHB-UVLO gate voltage.

The device enters and exits Bypass mode when the conditions in table Bypass Mode Entry, Exit are met.

Table 6-7 Bypass Mode Entry, Exit
Operation Mode Bypass Conditions
DEM / FPWM Entry VOUT < VI − 100mV and
VCOMP < VCOMP-MIN + 100mV
DEM Exit VCOMP > VCOMP-MIN + 100mV or
VCSP − VCSN < VZCD_BYP
FPWM Exit VCOMP > VCOMP-MIN + 100mV or
VCSP − VCSN < VNCLTH
LM5126A-Q1 Bypass Mode Entry, Exit Figure 6-9 Bypass Mode Entry, Exit