SNVSCO1 November   2025 LM5126A-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin )
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP, CSN)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP, CSN)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 3 Phase Operation
      3. 7.1.3 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 AC Loop Response Curve
        5. 7.2.3.5 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Feedback Compensation

The open-loop response of a boost regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain. The modulator transfer function of a current mode boost regulator includes a power stage transfer function with an embedded current loop. The transfer function is simplified as one pole, one zero, and one right-half-plane zero (RHPZ) system.

The modulator transfer function is defined as follows:

Equation 24. v^outv^comp=AM×1+sωZ_ESR1-sωRHPZ1+sωP_LF×GACB(s)

where

  • Modulator DC gain, AM=Rout×D'2×Acs×Rcs_eq
  • Load pole, ωP_LF=2Rout×Cout
  • ESR zero, ωZ_ESR=1RESR×Cout
  • RHPZ, ωRHPZ=Rout×D'2Lm_eq
  • The equivalent load resistance, Rout=Vout2Pout_total
  • The equivalent inductance, Lm_eq=LmNp
  • The equivalent current sense resistor, Rcs_eq=RcsNp
  • Np is the number of the phases.
  • Active current balancing circuit gain, GACBs=12×s×4×10-6+1s×2×10-6+1. An active current balancing circuit is employed in LM5126A-Q1 to reduce the average current error caused by the difference of the two inductors.

If the equivalent series resistance (ESR) of Cout (RESR) is small enough and the RHPZ frequency is far away from the target crossover frequency, the modulator transfer function is further simplified to a one pole system and the voltage loop is closed with only two loop compensation components, RCOMP and CCOMP, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

As shown in Figure 7-1, a gm amplifier is utilized as the output voltage error amplifier. The feedback transfer function includes the feedback resistor divider gain and loop compensation of the error amplifier. RCOMP, CCOMP, and CHF configure the error amplifier gain and phase characteristics, create a pole at origin, a low frequency zero and a high frequency pole.

LM5126A-Q1 Type II gm Amplifier CompensationFigure 7-1 Type II gm Amplifier Compensation

Feedback transfer function is defined as follows:

Equation 25. -v^compv^out=AVM×ωZ_EAs×1+sωZ_EA1+sωP_EA

where

  • The middle-band voltage gain, AVM=KFB×gm×RCOMP
  • gm = 1mA/V.
  • The feedback resistor divider gain KFB=RFBBRFBT+RFBB. KFB=130 for the internal feedback resistor divider.
  • Low frequency zero, ωZ_EA=1RCOMP×CCOMP
  • High frequency pole, ωP_EA1RCOMP×CHF

The pole at the origin minimizes the output steady state error. Place the low frequency zero to cancel the load pole of the modulator. Use the high frequency pole to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost is achieved at the crossover frequency. Place the high frequency pole beyond the crossover frequency because the addition of CHF adds a pole in the feedback transfer function.

The crossover frequency (open loop bandwidth) is usually limited to one fifth of the RHPZ frequency.

Increase RCOMP and proportionally decreasing CCOMP for higher crossover frequency. Conversely, decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function.