SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.5.1 Push-Pull Outputs

The pull-up voltage for the push-pull outputs is externally provided by the user. PULL_UP1 (input) is the pull-up voltage domain for all RESETx outputs (RESET1 to RESET4), while PULL_UP2 (input) is the pull-up voltage domain for the PWRGD and WDO outputs. Refer to Figure 8-10 to Figure 8-13.

Note: There are no sequencing requirements for IN, PULL_UP1, and PULL_UP2.

Each output stage consists of a high side PMOS and low side NMOS (CMOS) pair. The PMOS resistance is typically 9Ω (max of 20Ω) while the NMOS is 16Ω typically (max of 36Ω), when VPULL_UPx ≥ 3.3V. PULL_UP1 and PULL_UP2, have a voltage range of 1.6V to 7V, and can be independently biased or tied to the same voltage rail, however both most be biased. The output resistance of the PMOS leg has a PULL_UPx voltage dependency. The lower the PULL_UPx voltage, the higher the PMOS resistance.

When VIN < VPOR_IN (2V maximum) or VPULL_UPx > VPOR_PULL_UPx (1.1V maximum) the output are in a known pull-down state. At this condition the outputs have reduced sinking capabilities with VOL ≤ 320mV when the device is sinking 100μA of current into the outputs:

  • RESETx
  • PWRGD
  • WDO

Once the input voltage range is within the recommended input voltage range of 3V to 14V, the outputs have the full strength capabilities of ±10mA, per output.

TPS7H3024-SP RESETx Push-Pull Output Stages for UV Channel Type Figure 8-10 RESETx Push-Pull Output Stages for UV Channel Type
TPS7H3024-SP WDO Push-Pull Output Stage for UV Channel Type Figure 8-12 WDO Push-Pull Output Stage for UV Channel Type
TPS7H3024-SP PWRGD Push-Pull Output Stage for UV Channel Type Figure 8-11 PWRGD Push-Pull Output Stage for UV Channel Type
TPS7H3024-SP RESETx Push-Pull Output Stages for OV Channel Type
A. Only the RESETx are dependent on the type of channel as: UV or OV. This is dependent in the logical value of the MODE input pin.
Figure 8-13 RESETx Push-Pull Output Stages for OV Channel Type