SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.7.2 WD_TMR

The WD_TMR is an adjustable timer that programs the time-out of the internal watchdog timer. The watchdog timer is commonly used to monitor coherent processor execution. If the monitored processor is halted due to a fault, the WDI pin will not detect a rising edge resulting in asserting the WDO low, hence resetting the processor to a known state. A typical connection between the monitored processor and the TPS7H3024 is shown in Figure 8-15. Figure 8-16 shows the correct and incorrect (late pulse) handshake between the processor and the watchdog in the TPS7H3024.

The user can program the WD_TMR using a single resistor between the WD_TMR pin and GND. The range of the resistor (RWD) is between 56.2kΩ to 174kΩ, for a time of 520ms to 1.5s, respectively. If the user does not want to use the watchdog timer, the pin can be left floating. Disabling the watchdog timer reduces the quiescent (IQ_IN) current of the device.

Note: When the watchdog timer is disabled (by floating the WD_TMR pin), WDO is equal to PWRGD.

The REG_TMR resistor can be selected using Equation 24. Figure 8-17 shows the linear trend between the WD_TMR resistor and the allowed time to clear the watchdog timer (or time-out).

Equation 24. R WD _ T M R ( k Ω ) = 114.5 × t WD _ T M R   ( s ) - 3.5

Table 8-3 shows typical resistor values for different allowed regulation times. The WDI pin minimum pulse width is specified as twice the watchdog oscillator period. The oscillator period can be calculated using Equation 25.

Equation 25. tWD_OSC(s)= tWD_TMR(s)57,344
TPS7H3024-SP Watchdog timer typical handshake between TPS7H3024 and monitored processor Figure 8-15 Watchdog timer typical handshake between TPS7H3024 and monitored processor
TPS7H3024-SP Watchdog Timing Diagram Figure 8-16 Watchdog Timing Diagram
Table 8-3 Typical REG_TMR Resistors
Allowed Regulation Time (s) RREG_TMR (kΩ)
0.52 56.2
1 118
1.5 174
TPS7H3024-SP RWD_TMR vs tWD_TMR Across Full Oscillator Range Figure 8-17 RWD_TMR vs tWD_TMR Across Full Oscillator Range