SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4 Device Functional Modes

Table 8-4 RESETx, PWRGD and WDO Truth Table when VIN and VPULL_UPx is Lower than the Recommended Minimum Voltage.
SR_UVLO(1)(2) SENSEx
(3)(4)		 RESETx PWRGD WDO IN PULL_UPx
0 or 1 0 or 1 Undetermined Undetermined Undetermined VIN < VPOR_IN VPULL_UPx< VPOR_PULL_UPx
L L L VIN < VPOR_IN VPOR_PULL_UPx< VPULL_UPx < 1.6V
L L L VPOR_IN < VIN < 3V VPULL_UPx< VPOR_PULL_UPx
L L L VPOR_IN < VIN < 3V 1.6V < VPULL_UPx < 7V
Table 8-5 RESETx, PWRGD and WDO Truth Table when VIN and VPULL_UPx is within Recommended Operating Voltages
SR_UVLO(1)(2) MODE
(5)(6)		 SENSE1
(3)(4)		 SENSE2
(3)(4)		 SENSE3
(3)(4)		 SENSE4
(3)(4)		 RESET1 RESET2 RESET3 RESET4 PWRGD WDO
(7)
0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 L L L L L L
1 0 0 0 0 0 L H L H L L
0 0 0 1 L H L L L L
0 0 1 0 L H H H L L
0 0 1 1 L H H L L L
0 1 0 0 L L L H L L
0 1 0 1 L L L L L L
0 1 1 0 L L H H L L
0 1 1 1 L L H L L L
1 0 0 0 H H L H L L
1 0 0 1 H H L L L L
1 0 1 0 H H H H H H
1 0 1 1 H H H L L L
1 1 0 0 H L L H L L
1 1 0 1 H L L L L L
1 1 1 0 H L H H L L
1 1 1 1 H L H L L L
1 0 0 0 0 L H L H L L
0 0 0 1 L H L L L L
0 0 1 0 L H H H L L
0 0 1 1 L H L L L L
0 1 0 0 L L L H L L
0 1 0 1 L L L L L L
0 1 1 0 L L H H L L
0 1 1 1 L L L L L L
1 0 0 0 H H L H L L
1 0 0 1 H H L L L L
1 0 1 0 H H H H H H
1 0 1 1 H H L L L L
1 1 0 0 L L L H L L
1 1 0 1 L L L L L L
1 1 1 0 L L H H L L
1 1 1 1 L L L L L L
(1) 0 = VSR_UVLO < VTH_SR_UVLO_FALLING
(2) 1 = VSR_UVLO > VTH_SR_UVLO_RISING
(3) 0 = VSENSEx < VTH_SENSEx
(4) 1 = VSENSEx > VTH_SENSEx
(5) 0 = VMODE < VTH_MODE_FALLING
(6) 1 = VMODE > VTH_MODE_RISING
(7) Assuming a valid rising edge pulse in WDI before the Watchdog timer is expired.