SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.1.1 Design Requirements

This design requires monitoring two voltage rails using window comparators to make sure of reliable operation. As window supervision is used, the upper and lower system specification bounds are monitored. Additionally, coherent processor execution is monitored using the watchdog. The supervisor IC is set to start around 86% (or 10.31V) of the nominal 12V rail, using an external resistive divider driving the SR_UVLO pin.

All flags are assumed to be monitored by a house-keeping processor, and the WDO is used to drive the non-maskable interrupt of the processor. All design conditions are defined in Table 9-1.

Table 9-1 Design Conditions
PARAMETERDESIGN REQUIREMENTDESIGN RESULT
System nominal voltageMonitor the 12V input voltage to the supervisor and enable the IC when the voltage is greater than 10.3V (86%) for at least 2.8ms. When the voltage decrements below 8.5V (or 71%) the system is disabled. The TPS7H3024 can be externally enabled accurately by using the SR_UVLO . The internal reference is accurate to 3.1% across temperature, voltage and TID. For minimal error, users are recommended to use 0.1% tolerance resistors.
VOUT1= 3.3V (nominal)Undervoltage with:

VOUT1_RISE_UV = 98% and
VOUT1_FALL_UV = 95%

VOUT1_RISE_UV = 3.25V

VOUT1_FALL_UV = 3.15V

Overvoltage with:

VOUT1_RISE_OV = 105% and
VOUT1_FALL_OV = 102%

VOUT1_RISE_OV = 3.45V

VOUT1_FALL_OV = 3.35V

VOUT2=1.8V (nominal)Undervoltage with:

VOUT2_RISE_UV = 98% and
VOUT2_FALL_UV = 97%

VOUT2_RISE_UV = 1.77V

VOUT2_FALL_UV = 1.75V

Overvoltage with:

VOUT2_RISE_OV = 103% and
VOUTx_FALL_OV = 102%

VOUT2_RISE_OV = 1.86V

VOUT2_FALL_OV = 1.84V

RESETx delay during the out-of-fault state Delay of 260μs nominalRDLY_TMR = 10.5kΩ
Watchdog timeout1 second nominalRWD_TMR = 118kΩ