SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Over 3V ≤ VIN ≤ 14V, RDLY_TMR = 10kΩ, RWD_TMR = 56.2kΩ, VPULL_UP1 = 3.3V, VPULL_UP2 = 3.3V, over temperature range (TA= –55°C to 125°C), unless otherwise noted; includes group E radiation testing at TA = 25°C for QML RHA devices (1) (2) 
PARAMETER TEST CONDITIONS SUB-GROUP (3) MIN TYP MAX UNIT
SUPPLY VOLTAGES AND CURRENTS
IQ_IN  VIN quiescent current VSR_UVLO > VTH_SR_UVLO_RISING (MAX)   1, 2, 3 1.5 2.5 mA
ISD_IN VIN shutdown current VSR_UVLO = 0V 1, 2, 3 1.5 2.1
UVLORISE VIN rising undervoltage lockout 1, 2, 3 2.73 2.80 2.88 V
UVLOFALL VIN falling udervoltage lockout 1, 2, 3 2.58 2.65 2.72
VLDO Internal linear regulator output voltage 4V ≤ VIN ≤ 14V 1, 2, 3 3.23 3.29 3.37 V
VIN = 3V 1, 2, 3 98% 99% × VIN
VLDOI_MAX VLDO maximum current  3.65V ≤ VIN ≤ 14V,
VLDO= 98.5% x VLDO(NOM)		 1, 2, 3 5 mA
REFCAP Internal bandgap voltage 1, 2, 3 1.188 1.2 1.212 V
VPOR_IN IN power on reset voltage (4) 1.6V ≤ VPULL_UPx ≤ 7V,
VOL ≤ 320mV with IRESETx = –1mA		 1, 2, 3 1.42 2
VPOR_PULL_UPx PULL_UPx power on reset voltage (5) VIN = 0V, VOL ≤ 320mV,
IRESETx = –100µA		 1, 2, 3 0.85 1.1
VHYS HYS pin internal voltage RHYS = 49.9kΩ 1, 2, 3 1.164 1.2 1.236
SENSE1 TO SENSE4, SR_UVLO, WDI AND MODE COMPARATOR INPUTS
VTH_SENSEx Threshold voltage at SENSEx  1, 2, 3 593.1 599.7 604.9 mV
IHYS_SENSEx SENSEx hysteresis current VSENSEx = 700mV 1, 2, 3 23.28 24 24.72 µA
ILKG_SENSEx Input leakage current at SENSEx VSENSEx = 500mV 1, 2, 3 1 100 nA
VTH_SR_UVLO_RISING Rising threshold voltage at SR_UVLO 1, 2, 3 580 602 618 mV
VTH_SR_UVLO_FALLING Falling threshold voltage at SR_UVLO 1, 2, 3 475 499 517
ILKG_SR_UVLO Input leakage current at SR_UVLO VSR_UVLO = 7V 1, 2, 3 2 100 nA
VTH_WDI_RISING Rising threshold voltage at WDI 1, 2, 3 578 602 624 mV
VTH_WDI_FALLING Falling threshold voltage at WDI 1, 2, 3 473 498 521 mV
ILKG_WDI Input leakage current at WDI VWDI = 7V 1, 2, 3 1.4 100 nA
VTH_MODE_RISING Rising threshold voltage at MODE 1, 2, 3
7, 8		 576 600 623 mV
VTH_MODE_FALLING Falling threshold voltage at MODE 1, 2, 3
7, 8		 475 498 520 mV
ILKG_MODE Input leakage current at MODE VMODE = 7V 1, 2, 3 1 100 nA
RESET1 TO RESET4, PWRGD AND WDO PUSH PULL OUTPUTS
PULL_UPxLKG PULL_UPx leakage current VPULL_UPx = 7V, RESETx= LOW 1, 2, 3 48 100 µA
VOL_RESETx Low-level RESETx output voltage 1.6V ≤ VPULL_UP1 ≤ 7V ILOAD = –2mA 1, 2, 3 5% x VPULL_UP1
ILOAD = –10mA
1, 2, 3

 23%
VOH_RESETx High-level RESETx output voltage 1.6V ≤ VPULL_UP1 ≤ 7V ILOAD = 2mA 1, 2, 3 95%
ILOAD = 10mA
1, 2, 3

 75%
VOL_PWRGD Low-level PWRGD output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = –2mA 1, 2, 3 5% x VPULL_UP2
ILOAD = –10mA
1, 2, 3

 23%
VOH_PWRGD High-level PWRGD output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = 2mA 1, 2, 3 95%
ILOAD = 10mA
1, 2, 3

 75%
VOL_WDO Low-level WDO output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = –2mA 1, 2, 3 5%
ILOAD = –10mA
1, 2, 3

 23%
VOH_WDO High-level WDO output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = 2mA 1, 2, 3 95%
ILOAD = 10mA
1, 2, 3

 75%
SRRESETx_RISE RESETx rising output voltage slew rate 10% to 90% of VPULL_UP1,
RLOAD = 50kΩ,
CLOAD = 100pF		 1.6V ≤ VPULL_UP1 ≤ 7V 7, 8
9, 10, 11		 17 298 V/µs
SRPWRGD_RISE PWRGD rising output voltage slew rate 7, 8
9, 10, 11
17		 298
SRWDO_RISE WDO rising output voltage slew rate 7, 8
9, 10, 11		 17 298
SRRESETx_FALL RESETx falling output voltage slew rate 90% to 10% of VPULL_UP1,
RLOAD = 50kΩ,
CLOAD = 100pF		 1.6V ≤ VPULL_UP1 ≤ 7V 7, 8
9, 10, 11		 44 186
SRPWRGD_FALL PWRGD falling output voltage slew rate 7, 8
9, 10, 11		 44 186
SRWDO_FALL WDO falling output voltage slew rate 7, 8
9, 10, 11		 44 186
RRESETx_PULL_UP RESET PMOS source output resistance ILOAD = 2mA 1.6V ≤ VPULL_UP1 < 3.3V 1, 2, 3 20 40 Ω
3.3V ≤ VPULL_UP1 ≤ 7V
1, 2, 3

 9 20
RPWRGD_PULL_UP PWRGD PMOS source output resistance ILOAD = 2mA 1.6V ≤ VPULL_UP2 < 3.3V 1, 2, 3 20 40
3.3V ≤ VPULL_UP2 ≤ 7V
1, 2, 3

 9 20
RWDO_PULL_UP WDO PMOS source output resistance ILOAD = 2mA 1.6V ≤ VPULL_UP2 < 3.3V 1, 2, 3 20 40
3.3V ≤ VPULL_UP2 ≤ 7V
1, 2, 3

 9 20
RRESETx_PULL_DOWN RESET NMOS sink output resistance ILOAD = –2mA, 1.6V ≤ VPULL_UP1 ≤ 7V 1, 2, 3 16 36
RPWRGD_PULL_DOWN PWRGD NMOS sink output resistance ILOAD = –2mA, 1.6V ≤ VPULL_UP1 ≤ 7V 1, 2, 3 16 36
RWDO_PULL_DOWN WDO NMOS sink output resistance ILOAD = –2mA, 1.6V ≤ VPULL_UP1 ≤ 7V
1, 2, 3

 16 36
THERMAL PROTECTION
TSD_ENTER Thermal shutdown enter temperature 185 ℃
TSD_EXIT Thermal shutdown exit temperature 171
DELAY AND WATCHDOG TIMERS
tDLY_TMR Delay time  RDLY_TMR = 10.5kΩ  1, 2, 3 0.22 0.26 0.33 ms
RDLY_TMR = 619kΩ  1, 2, 3 11.3 12.5 13.7
RDLY_TMR = 1.18MΩ  1, 2, 3 21.3 23.7 26.2
tWD_TMR Watchdog time-out RWD_TMR = 56.2kΩ  1, 2, 3 0.43 0.52 0.57 s
RWD_TMR = 118kΩ  1, 2, 3 0.8 1 1.2
RWD_TMR = 174kΩ 1, 2, 3 1.34 1.5 1.7
(1) See the 5962R24206 SMD (standard microcircuit drawing) for additional information on the RHA devices.
(2) All voltage values are with respect to GND.
(3) For subgroup definitions, see Quality Conformance Inspection table.
(4) VPOR_IN is the minimum VIN voltage for a controlled output state, when 1.6V ≤ VPULL_UPx ≤ 7V. Below VPOR_IN, the output state cannot be determined.
(5) VPOR_PULL_UPx is the minimum VPULL_UPx voltage for a controlled output state, when VIN ≤ 3V. Below VPOR_PULL_UPx the output state cannot be determined.