SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
9.2.1.2.2 SR_UVLO Threshold

In this application the SR_UVLO pin is used to monitored the input voltage supply of 12V and enable the device when the desired voltage is reach.

The IC is enabled when the rail voltage is greater than 10.26V (or 85.5% of the nominal voltage, typically). The falling voltage is not controlled as the hystersis voltage on the SR_UVLO is internally controlled. However is calculated to be 8.55V (or 71.2% of the nominal voltage, typically). As the TPS7H3024 has an internal time constant (tStart_up_delay) of 2.8ms (max), a delay capacitor of 3.3μF is added to SR_UVLO pin. This capacitor is added to introduce a delay in the SR_UVLO pin when VIN is rising. This capacitor adds a second condition to start the sequence up, if VIN ≥ 10.26V (typ) for at least 2.8ms then the IC is enabled.

Fixing the upper resistor for the resistive divider in SR_UVLO, we can calculate the bottom resistor per our design requirements. The upper resistor is fixed to 10kΩ. Using the equation in Equation 1 the bottom resistor is calculated as:

Equation 26. V B O T T O M _ S R _ U V L O _______ =   10 k Ω   × 0.599 V 10.26 V - 0.599 V = 620 Ω

Now that the reference resistor is calculated, we can select the actual (or real) resistor. In this case a 0.1% tolerance resistor is used to select the closest value (in this specific case the reference and real resistor is the same)

  • RBOTTOM_SR_UVLO = 620Ω

With the actual resistor values, we can back-calculate the rising and falling voltages that enables and disables the supervisor, respectively. Using Equation 3 and Equation 4 as:

Equation 27. V IN _ UVLO_RISING_NOMINAL   ( V ) = 1   +   10   k Ω 620   Ω   ×   0.599   V   ≅   10.26   V  
Equation 28. V IN _ UVLO_FALLING_NOMINAL   ( V ) = 1   +   10   k Ω 620   Ω   ×   0.496   V   ≅   8.50   V  

The delay capacitor is calculated using Equation 7, Equation 8 and Equation 6 as:

Equation 29. R T H   ( Ω ) = 10   k Ω × 620   Ω 10   k Ω + 620   Ω   =   583.80   Ω
Equation 30. V T H   ( Ω ) = 620   Ω 10   k Ω + 620   Ω ×   12   V   =   0.70   V
Equation 31. C D E L A Y   ( F ) ≥ 0.0028   s 582.8   Ω   × l n - 0.7   V 0.599   V - 0.7   V   =   2.48   µ F

The delay capacitor is selected as 3.3μF.