SNVSCS7D April   2025  – November 2025 TPSM33606-Q1 , TPSM33610-Q1 , TPSM33620-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Output Voltage Selection
        1. 7.3.2.1 Adjustable Output Voltage Variants
        2. 7.3.2.2 Fixed Output Voltage Variants
      3. 7.3.3  Enable, Start-Up, and Shutdown
        1. 7.3.3.1 External UVLO through the EN Pin
      4. 7.3.4  External CLK SYNC
        1. 7.3.4.1 Pulse-Dependent MODE/SYNC Pin Control
      5. 7.3.5  Power-Good Output Operation
      6. 7.3.6  Internal LDO, VCC and VOUT/FB Input
      7. 7.3.7  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Recovery from Dropout
      10. 7.3.10 Overcurrent Protection (Hiccup Mode)
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 VCC
        6. 8.2.2.6 CFF Selection
        7. 8.2.2.7 Power-Good Signal
        8. 8.2.2.8 Maximum Ambient Temperature
        9. 8.2.2.9 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
      3. 9.1.3 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RDN Package, 11-Pin QFN-FCMOD, Top View (All Variants)
Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 PGOOD A Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10kΩ to 100kΩ pullup resistor is required for an excellent pullup voltage. If not used, this pin can be left open or connected to GND. High = power OK, Low = power bad. PGOOD pin goes low when EN = Low.
2 EN A Precision enable input pin. High = ON, Low = OFF. Precision enable allows the pin to be used as an adjustable UVLO. Can be connected directly to VIN. The module can be turned off by using an open-drain or collector device to connect this pin to GND. Place an external voltage divider between VIN, this pin, and GND to create an external UVLO. Do not float this pin.
3 VIN P Input supply voltage. Connect the input supply to these pins. Connect a high-quality bypass capacitor or capacitors directly to this pin and GND in close proximity to the module. Refer to Section 8.5.2 for input capacitor placement example.
4 VOUT P Output voltage. The pin is connected to the integrated filter inductor. Connect the pin to the output load and connect external output capacitors between this pin and GND. Fixed output options are available. For fixed output variants, connect the FB pin to VOUT. Check Section 4 for more details.
5, 6 SW P Power module switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.
7 BOOT P Bootstrap pin for internal high-side driver circuitry. A 100nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage.
8 VCC P Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1µF capacitor from this pin to GND.
9 FB A Feedback input. For the adjustable output, connect the mid-point of the output voltage feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to GND. When connecting with feedback resistor divider, keep this FB trace short and as small as possible to avoid noise coupling. See Section 8.5.2 for a feedback resistor placement. For a fixed output configuration, connect FB pin 9 directly to VOUT pin 4. Do not leave open or connect to GND
10 GND G Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces.
11 MODE/SYNC A The part can operate in user-selectable auto/FPWM operation based on the voltage at MODE/SYNC pin. The part can also be synchronized to an external clock. Clock triggers on rising edge of applied external clock. Do not float this pin.
(1) A = Analog, P = Power, G = Ground