SNVSCS7D April   2025  – November 2025 TPSM33606-Q1 , TPSM33610-Q1 , TPSM33620-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Output Voltage Selection
        1. 7.3.2.1 Adjustable Output Voltage Variants
        2. 7.3.2.2 Fixed Output Voltage Variants
      3. 7.3.3  Enable, Start-Up, and Shutdown
        1. 7.3.3.1 External UVLO through the EN Pin
      4. 7.3.4  External CLK SYNC
        1. 7.3.4.1 Pulse-Dependent MODE/SYNC Pin Control
      5. 7.3.5  Power-Good Output Operation
      6. 7.3.6  Internal LDO, VCC and VOUT/FB Input
      7. 7.3.7  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Recovery from Dropout
      10. 7.3.10 Overcurrent Protection (Hiccup Mode)
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light-Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light-Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 VCC
        6. 8.2.2.6 CFF Selection
        7. 8.2.2.7 Power-Good Signal
        8. 8.2.2.8 Maximum Ambient Temperature
        9. 8.2.2.9 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
      3. 9.1.3 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Limits apply over TJ = –40°C to 150°C, VIN = 13.5V, VOUT = 3.3V, FSW = 2.2MHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VIN Input voltage rising threshold Before start-up 3.2 3.35 3.5 V
Once Operating 2.45 2.7 3 V
IQ_VIN Input operating quiescent current (non-switching)  TA = 25°C, VEN = 3.3V, VFB = 1.5V 1.2 µA
ISDN_VIN VIN shutdown quiescent current VEN = 0V, TA = 25°C 0.3 µA
ENABLE
VEN_RISE EN voltage rising threshold 1.16 1.23 1.3 V
VEN_FALL EN voltage falling threshold 0.81 0.9 0.97 V
VEN_HYS EN voltage hysteresis 0.275 0.353 0.404 V
VEN_WAKE EN wake-up threshold 0.5 0.7 1 V
ILKG-EN Enable pin input leakage current VEN = VIN  = 24V 10 nA
INTERNAL LDO VCC
VCC Internal LDO VCC output voltage VFB = 0V, IVCC = 1mA 3.1 3.3 3.5 V
FEEDBACK
VFB Internal reference voltage accuracy Over the VIN range, VOUT = 1V, FPWM mode, FSW = 2.2MHz 0.99 1 1.01 V
VOUT_ACC_3V3 Output voltage accuracy for fixed 3.3V VOUT trim option Over the VIN range, FPWM mode, FSW = 2.2MHz 3.27 3.3 3.33 V
VOUT_ACC_5V0 Output voltage accuracy for fixed 5V VOUT trim option Over the VIN range, FPWM mode, FSW = 2.2MHz 4.95 5 5.05 V
IFB Input current into FB pin Adjustable configuration, VFB = 1V 10 nA
CURRENT LIMITS
IL_HS High-side switch current limit (TPSM33620-Q1) Duty cycle approaches 0% 3.4 4 4.6 A
IL_LS Low-side switch current limit  (TPSM33620-Q1) 1.9 2.2 2.53 A
IL_NEG Negative current limit (TPSM33620-Q1) –1 –0.8 –0.6 A
IL_HS High-side switch current limit  (TPSM33610-Q1) Duty cycle approaches 0% 1.7 2 2.3 A
IL_LS Low-side switch current limit  (TPSM33610-Q1) 0.85 1.1 1.4 A
IL_NEG Negative current limit (TPSM33610-Q1) –1 –0.8 –0.6 A
IL_HS High-side switch current limit  (TPSM33606-Q1) Duty cycle approaches 0% 1.5 1.8 2.1 A
IL_LS Low-side switch current limit  (TPSM33606-Q1) 0.85 1.1 1.4 A
IL_NEG Negative current limit (TPSM33606-Q1) –1 –0.8 –0.6 A
IZC Zero-cross current limit  Auto mode 80 mA
VHICCUP Voltage on the FB pin below which module enters into hiccup mode Not during soft start 0.4 V
tW Short-circuit wait time ("hiccup" time before soft start)(1) 30 50 75 ms
SOFT-START
tSS Time from first SW pulse to VREF at 90% VIN ≥ 4.2V 2 3.5 4.6 ms
POWER GOOD
PGOV PG upper threshold - rising % of VOUT setting 104 108 111 %
PGUV PG lower threshold - falling % of VOUT setting 89 91 94.2 %
PGHYS PG upper threshold hysteresis for OV % of VOUT setting 1.8 2 2.4 %
PG upper threshold hysteresis for UV % of VOUT setting 1.8 3 4.7 %
VIN_PG_VALID Input voltage for valid PG output RPGD_PU = 10kΩ, VEN = 0V 1.5 V
VPG_LOW Low level PG function output voltage 2mA pullup to PG pin, VEN = 3.3V 0.4 V
tPG_FLT_RISE Delay time to PG high signal 1.35 2.5 4 ms
tRESET_FILTER PGOOD deglitch delay at falling edge 25 47 75 µs
RPGD PGOOD ON resistance VEN = 3.3V, 200µA pullup current 100 Ω
RPGD PGOOD ON resistance VEN = 0V, 200µA pullup current 100 Ω
SWITCHING FREQUENCY
fSW Switching frequency 2.1 2.2 2.3 MHz
fSYNC_RANGE Switching frequency range by SYNC 1.9 2.5 MHz
DeltaFc Frequency increase/decrease from spread spectrum of internal oscillator Dual Random Spread Spectrum ±4 %
SYNCHRONIZATION
VMODE_L SYNC/MODE input voltage low level threshold 1 V
VMODE_H SYNC/MODE input voltage high level threshold 1.6 V
tPULSE_H High duration needed to be recognized as a pulse 100 ns
tPULSE_L Low duration needed to be recognized as a pulse 100 ns
tB Blanking of EN after rising or falling edges(1) 4 28 µs
tSYNC High/low level pulse maximum duration to be recognized as a valid clock signal 6 µs
POWER STAGE
VBOOT_UVLO Voltage on BOOT pin compared to SW which turns off high-side switch 2.1 V
tON_MIN Minimum HS switch ON pulse width(1) FPWM mode, VOUT = 1V, IOUT = 1A 65 75 ns
tON_MAX Maximum HS switch ON pulse width(1) HS timeout in dropout 6 9 13 µs
tOFF_MIN Minimum HS switch OFF pulse width VIN = 4V, IOUT = 1A 60 85 ns
RDSON-HS High-side MOSFET on-resistance Load = 1A 132 260 mΩ
RDSON-LS Low-side MOSFET on-resistance Load = 1A 75 140 mΩ
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.