SPAU024 April   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Configuration 1: Standalone Configuration
      2. 2.1.2 Configuration 2: AM26x controlCARD Backward Compatibility Configuration
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Tree
      2. 2.2.2 Power Sequence
      3. 2.2.3 Power Status LEDs
      4. 2.2.4 PMIC
    3. 2.3  Header Information
      1. 2.3.1 Baseboard Headers (J1, J2, J3)
      2. 2.3.2 XDS Debug Header (J4)
      3. 2.3.3 MIPI-60 Header (J5)
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  Interfaces
      1. 2.9.1 Memory Interface
        1. 2.9.1.1 OSPI
        2. 2.9.1.2 Board ID EEPROM
      2. 2.9.2 I2C
      3. 2.9.3 SPI
      4. 2.9.4 UART
      5. 2.9.5 JTAG
      6. 2.9.6 TRACE
      7. 2.9.7 ADC and DAC
      8. 2.9.8 Off-SOM Peripherals
        1. 2.9.8.1 MCAN
        2. 2.9.8.2 LIN
        3. 2.9.8.3 FSI
        4. 2.9.8.4 USB
        5. 2.9.8.5 Ethernet
          1. 2.9.8.5.1 RGMII
          2. 2.9.8.5.2 PRU-ICSS
    10. 2.10 Test Points
    11. 2.11 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References

1.4 Device Information

The AM261x Sitara Arm® Microcontrollers are part of Sitara AM26x real-time MCU families designed to meet the complex real-time processing needs of next generation industrial and automotive embedded products. With scalable Arm® Cortex®-R5F performance and an extensive set of peripherals, AM261x device is designed for a broad range of applications while offering safety features and optimized peripherals for real time control.

Key features and benefits:

  • Peripherals supporting system level connectivity such as Gigabit Ethernet, USB, OSPI/QSPI, CAN, UARTs, SPI and GPIOs.
  • Granular firewalls managed by Hardware Security Manager (HSM) enable developers to implement stringent security minded system design requirements.
  • Up to two R5F cores in cluster with 256KB of shared Tightly Coupled Memory (TCM) per core along with 1.5MB of shared SRAM, greatly reducing the need for external memory.