SPAU024 April   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Configuration 1: Standalone Configuration
      2. 2.1.2 Configuration 2: AM26x controlCARD Backward Compatibility Configuration
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Tree
      2. 2.2.2 Power Sequence
      3. 2.2.3 Power Status LEDs
      4. 2.2.4 PMIC
    3. 2.3  Header Information
      1. 2.3.1 Baseboard Headers (J1, J2, J3)
      2. 2.3.2 XDS Debug Header (J4)
      3. 2.3.3 MIPI-60 Header (J5)
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  Interfaces
      1. 2.9.1 Memory Interface
        1. 2.9.1.1 OSPI
        2. 2.9.1.2 Board ID EEPROM
      2. 2.9.2 I2C
      3. 2.9.3 SPI
      4. 2.9.4 UART
      5. 2.9.5 JTAG
      6. 2.9.6 TRACE
      7. 2.9.7 ADC and DAC
      8. 2.9.8 Off-SOM Peripherals
        1. 2.9.8.1 MCAN
        2. 2.9.8.2 LIN
        3. 2.9.8.3 FSI
        4. 2.9.8.4 USB
        5. 2.9.8.5 Ethernet
          1. 2.9.8.5.1 RGMII
          2. 2.9.8.5.2 PRU-ICSS
    10. 2.10 Test Points
    11. 2.11 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References

2.9.7 ADC and DAC

The AM261x controlSOM supports 18 ADC signal channels that are mapped from the AM261x SoC and terminated to the SOM HD Connector J1.

The signals with the _P and _N suffix are routed as differential pairs. For ADC0, the pairs are AIN2/AIN3 and AIN4/AIN5. For ADC1 and ADC2, the pairs are AIN0/1 and AIN2/3.

AM261-SOM-EVM ADC SOM Connections Figure 2-22 ADC SOM Connections

There is one mux (TMUX1136DQAR) that determines the routing of ADC signals to and from the SOM HD Connector.

Table 2-13 ADC MUX Select Logic
MUX Select Signal Condition Function Description
ADC0_AIN0/DAC_OUT_MUX_SEL SEL Signal HIGH S1A → D1 ADC0_AIN0 selected
SEL Signal LOW S1B → D1 DAC_OUT selected

ADC Switches

There are three switches that are used to configure the reference voltages for the ADC and DAC. Refer to Figure 2-24 for the on-board switch configuration.

AM261-SOM-EVM ADC Switch Routing Figure 2-23 ADC Switch Routing
  • The VREF Switch (S1) is a single pole double throw switch that controls which 1.8V reference is used for ADC and DAC.
    Table 2-14 VREF Switch
    VREF Switch Position Reference Selection
    Pin 1-2 (LEFT switch UP) EXT_VREF1 = PMIC LDO4 1.8V Reference (1V8_LDO4)
    Pin 2-3 (LEFT switch DOWN) EXT_VREF1 = SOM HD Connector VREF
    Pin 4-5 (RIGHT switch UP) EXT_VREF2 = PMIC_LDO4 1.8V Reference (1V8_LDO4)
    Pin 5-6 (RIGHT switch DOWN) EXT_VREF2 = SOM HD Connector VREF
  • The DAC VREF Switch (S2) is a single pole double throw switch that controls the input for the DAC VREF inputs of the AM261x SoC.
    Table 2-15 DAC VREF Switch
    DAC VREF Switch Position Reference Selection
    Pin 1-2 (LEFT) AM261x on-die LDO
    Pin 2-3 (RIGHT) Output of VREF Switch (EXT_VREF2)
  • The ADC VREF Switch (S4) contains two single pole double throw switches that control the input for the ADC VREF inputs of the AM263Px SoC.
    Note: S4.1 must be in the Pin 1-2 position and S4.2 must be in the pin 4-5 position for AM261x MCU+ SDK ADC Examples to function properly.
    Table 2-16 ADC VREF Switch
    ADC VREF Switch Position Reference Selection
    Pin 1-2 (LEFT switch UP) OPEN - Allow for reference to be AM261x on-die LDO reference
    Pin 2-3 (LEFT switch DOWN) Output of VREF Switch (EXT_VREF1)
    Pin 4-5 (RIGHT switch UP) OPEN - Allow for reference to be AM261x on-die LDO reference
    Pin 5-6 (RIGHT switch DOWN)3 Output of VREF Switch (EXT_VREF2)
AM261-SOM-EVM ADC, DAC VREF Switch Configuration Figure 2-24 ADC, DAC VREF Switch Configuration