SPAU024 April   2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Configuration 1: Standalone Configuration
      2. 2.1.2 Configuration 2: AM26x controlCARD Backward Compatibility Configuration
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Tree
      2. 2.2.2 Power Sequence
      3. 2.2.3 Power Status LEDs
      4. 2.2.4 PMIC
    3. 2.3  Header Information
      1. 2.3.1 Baseboard Headers (J1, J2, J3)
      2. 2.3.2 XDS Debug Header (J4)
      3. 2.3.3 MIPI-60 Header (J5)
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  Interfaces
      1. 2.9.1 Memory Interface
        1. 2.9.1.1 OSPI
        2. 2.9.1.2 Board ID EEPROM
      2. 2.9.2 I2C
      3. 2.9.3 SPI
      4. 2.9.4 UART
      5. 2.9.5 JTAG
      6. 2.9.6 TRACE
      7. 2.9.7 ADC and DAC
      8. 2.9.8 Off-SOM Peripherals
        1. 2.9.8.1 MCAN
        2. 2.9.8.2 LIN
        3. 2.9.8.3 FSI
        4. 2.9.8.4 USB
        5. 2.9.8.5 Ethernet
          1. 2.9.8.5.1 RGMII
          2. 2.9.8.5.2 PRU-ICSS
    10. 2.10 Test Points
    11. 2.11 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References

2.9.3 SPI

The AM261x controlSOM maps three SPI instances (SPI0, SPI1, SPI3) from the AM261x SoC to the SOM HD Connectors. Series termination resistors are placed near the SoC for each SPI clock signal. Each SPI instance is routed through a 4-channel FET switch that routes between the SOM HD connector and a specific peripheral or alternative header. Table 2-11 details the Muxing scheme on the SPI instances:

Table 2-11 AM261x controlSOM SPI Routing
SPI Instance B1 B2 Default
SPI0 SPI0 → SOM HD Connector J2 FSITX0 → SOM HD Connector J1 B1
SPI1 SPI1 → PMIC FSIRX0 → SOM HD Connector J1 B1
SPI3 SPI3 → SOM HD Connector J1 DAC_SPI3 → Emulation Header J7 B2

SPI0 is routed to the SOM HD connector J2 at the SPI standard location. The 4-channel FET switch can route the same AM261x device pins to the FSITX standard location on SOM HD connector J1 to be used as FSI signals.

SPI1 is routed to either the on-board PMIC (default selection) or as FSI signals to the FSIRX standard location on SOM HD connector J1.

SPI3 is routed to the standard SPI location on SOM HD connector J1 or to the Emulation Header (J7) to communicate with the DAC IC on the XDS110ISO-EVM (default selection).

AM261-SOM-EVM SPI Figure 2-17 SPI