SPAU024 April   2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Configuration 1: Standalone Configuration
      2. 2.1.2 Configuration 2: AM26x controlCARD Backward Compatibility Configuration
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Tree
      2. 2.2.2 Power Sequence
      3. 2.2.3 Power Status LEDs
      4. 2.2.4 PMIC
    3. 2.3  Header Information
      1. 2.3.1 Baseboard Headers (J1, J2, J3)
      2. 2.3.2 XDS Debug Header (J4)
      3. 2.3.3 MIPI-60 Header (J5)
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  Interfaces
      1. 2.9.1 Memory Interface
        1. 2.9.1.1 OSPI
        2. 2.9.1.2 Board ID EEPROM
      2. 2.9.2 I2C
      3. 2.9.3 SPI
      4. 2.9.4 UART
      5. 2.9.5 JTAG
      6. 2.9.6 TRACE
      7. 2.9.7 ADC and DAC
      8. 2.9.8 Off-SOM Peripherals
        1. 2.9.8.1 MCAN
        2. 2.9.8.2 LIN
        3. 2.9.8.3 FSI
        4. 2.9.8.4 USB
        5. 2.9.8.5 Ethernet
          1. 2.9.8.5.1 RGMII
          2. 2.9.8.5.2 PRU-ICSS
    10. 2.10 Test Points
    11. 2.11 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References

2.5 Reset

Figure 2-9 shows the reset architecture of the AM261x controlSOM.

AM261-SOM-EVM Reset Architecture Figure 2-9 Reset Architecture

The AM261x SoC has the following resets:

  • PORz is the Power-On-Reset for the MAIN Domain.
  • WARMRESETn is the Warm Reset to MAIN Domain.
AM261-SOM-EVM PORz Reset Signal Tree Figure 2-10 PORz Reset Signal Tree

The PORz signal is driven by a 3-input AND gate that generates a power on reset for the MAIN domain when:

  • The PMIC drives the NRES, MCU Reset output signal low.
  • The 1.2V buck regulator outputs a low signal for the power good signal.
  • The user push button (SW2) is pressed.

The PORz signal is tied to:

  • AM261x SoC PORz input
  • OSPI Flash Reset
  • BOOTMODE buffer output enable
  • SOM HD Connector J1

AM261-SOM-EVM WARMRESETn Reset Signal Tree Figure 2-11 WARMRESETn Reset Signal Tree

The WARMRESETn signal creates a warm reset to the MAIN domain when:

  • The user push button (SW4) is pressed.

The WARMRESETn signal is tied to:

  • AM261x SoC WARMRESETN output
  • RESETz signal created from push button + PMOS logic
  • IO Expander reset

The AM263Px Control Card also has an external interrupt to the SoC, INTn, that occurs when:

  • The user push button (SW3) is pressed.