SPAU024 April   2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Configuration 1: Standalone Configuration
      2. 2.1.2 Configuration 2: AM26x controlCARD Backward Compatibility Configuration
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Tree
      2. 2.2.2 Power Sequence
      3. 2.2.3 Power Status LEDs
      4. 2.2.4 PMIC
    3. 2.3  Header Information
      1. 2.3.1 Baseboard Headers (J1, J2, J3)
      2. 2.3.2 XDS Debug Header (J4)
      3. 2.3.3 MIPI-60 Header (J5)
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  Interfaces
      1. 2.9.1 Memory Interface
        1. 2.9.1.1 OSPI
        2. 2.9.1.2 Board ID EEPROM
      2. 2.9.2 I2C
      3. 2.9.3 SPI
      4. 2.9.4 UART
      5. 2.9.5 JTAG
      6. 2.9.6 TRACE
      7. 2.9.7 ADC and DAC
      8. 2.9.8 Off-SOM Peripherals
        1. 2.9.8.1 MCAN
        2. 2.9.8.2 LIN
        3. 2.9.8.3 FSI
        4. 2.9.8.4 USB
        5. 2.9.8.5 Ethernet
          1. 2.9.8.5.1 RGMII
          2. 2.9.8.5.2 PRU-ICSS
    10. 2.10 Test Points
    11. 2.11 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References

2.7 Boot Mode Selection

The bootmode for the AM261x is selected by a DIP switch (SW1). The supported boot modes are as shown in Table 2-7.

Table 2-7 Supported Boot Modes
Boot Mode or Peripheral Boot Media or Host Notes
OSPI-OSPI (4S), 50MHz, SDR, 0x6B Flash Memory ROM configures OSPI controller in QSPI 4S mode and downloads image from external flash, supports UART fallback boot mode if any failures.
UART, XMODEM, 115200bps External Host ROM configures UART0 with baud rate of 115200bps and downloads image from external PC terminal using x-modem protocol.
OSPI-OSPI (1S), 50MHz, SDR, 0x0B Flash Memory ROM configures OSPI controller in QSPI 1S mode and downloads image from external flash, supports UART fallback boot mode if any failures.
OSPI (8S), SDR, 33MHz, 0x8B Flash Memory ROM configures OSPI controller in 8S mode and downloads image from external flash, supports UART fallback boot mode if any failures.
xSPI (1S->8D) , 25MHz, SFDP QSPI Flash, External Host ROM configures OSPI controller in xSPI 8D mode ,Reads SFDP table for read command and downloads image from external flash, Flashes with SFDP are of JEDEC standard Rev D only supported.
USB DFU External Host ROM configures USB controller to work in device mode and download the image into L2 memory to process. In case of any failure, ROM falls back to UART boot mode. Supports USB 2.0 device mode at High-Speed (HS, 480Mbps)
DevBoot N/A No SBL. Used for development purposes only.
Table 2-8 Boot-Mode Selection Table
Boot Mode SW1.4, SOP3 SPI0_D0_pad SW1.3, SOP2 SPI0_CLK_pad SW1.2, SOP1 OSPI_D1 SW1.1, SOP0 OSPI_D0
OSPI-OSPI (4S), 50MHz, SDR, 0x6B 0 0 0 0
UART, XMODEM, 115200bps 0 0 0 1
OSPI-OSPI (1S), 50MHz, SDR, 0x0B 0 0 1 0
OSPI (8S), SDR, 33MHz, 0x8B 0 0 1 1
xSPI (1S->8D) , 25MHz, SFDP 1 1 0 0
USB DFU 1 1 1 0
DevBoot 1 0 1 1
Unsupported boot mode All other combinations not defined above.
AM261-SOM-EVM AM261-SOM-EVM Bootmode Switches Figure 2-13 AM261-SOM-EVM Bootmode Switches