SPAU024 April   2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Configuration 1: Standalone Configuration
      2. 2.1.2 Configuration 2: AM26x controlCARD Backward Compatibility Configuration
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Tree
      2. 2.2.2 Power Sequence
      3. 2.2.3 Power Status LEDs
      4. 2.2.4 PMIC
    3. 2.3  Header Information
      1. 2.3.1 Baseboard Headers (J1, J2, J3)
      2. 2.3.2 XDS Debug Header (J4)
      3. 2.3.3 MIPI-60 Header (J5)
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  Interfaces
      1. 2.9.1 Memory Interface
        1. 2.9.1.1 OSPI
        2. 2.9.1.2 Board ID EEPROM
      2. 2.9.2 I2C
      3. 2.9.3 SPI
      4. 2.9.4 UART
      5. 2.9.5 JTAG
      6. 2.9.6 TRACE
      7. 2.9.7 ADC and DAC
      8. 2.9.8 Off-SOM Peripherals
        1. 2.9.8.1 MCAN
        2. 2.9.8.2 LIN
        3. 2.9.8.3 FSI
        4. 2.9.8.4 USB
        5. 2.9.8.5 Ethernet
          1. 2.9.8.5.1 RGMII
          2. 2.9.8.5.2 PRU-ICSS
    10. 2.10 Test Points
    11. 2.11 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References
PRU-ICSS

The AM261x controlSOM makes use of two (out of the four) on-die programmable real-time unit and industrial communication subsystems (PRU-ICSS) of the AM261x SoC to interface with up to two Ethernet® ports. When using the AM261x controlSOM with the HSEC180ADAPEVM-AM2, the PR0_PRU0 signals are connected to a Gigabit Ethernet PHY transceiver (DP83869), and the PR0_PRU1 signals are connected to a 48-pin Ethernet Add-on Board Connector. The Ethernet Add-on Board connector allows Ethernet PHY PCBs from the TI Ethernet Add-on Board Ecosystem to be connected to the HSEC180ADAPEVM-AM2 and interfaced with using the AM261x controlSOM. For more information, see the AM261x SOM to HSEC Adapter Board User's Guide.

Signals from the PRU-ICSS PR0 core are connected to SOM HD Connector J3.

AM261-SOM-EVM PRU-ICSS Figure 2-30 PRU-ICSS
Note: The PRU-ICSS and AM261x GPIO signal mapping to MII Ethernet is given in Table 2-17 below. See the HSEC180ADAPEVM-AM2 User's Guide for more information and implementation details.
Table 2-17 AM261x controlSOM PRU-ICSS to MII Signal Mapping
MII Port AM261x controlSOM Signal MII Ethernet Mapping
MII0 PR0_PRU0_GPIO0 RXD0
PR0_PRU0_GPIO1 RXD1
PR0_PRU0_GPIO2 RXD2
PR0_PRU0_GPIO3 RXD3
PR0_PRU0_GPIO4 RX_DV
PR0_PRU0_GPIO5 RX_ER
PR0_PRU0_GPIO6 RX_CLK
PR0_PRU0_GPIO8 RX_LINK
PR0_PRU0_GPIO9 COL
PR0_PRU0_GPIO10 CRS
PR0_PRU0_GPIO11 TXD0
PR0_PRU0_GPIO12 TXD1
PR0_PRU0_GPIO13 TXD2
PR0_PRU0_GPIO14 TXD3
PR0_PRU0_GPIO15 TX_EN
PR0_PRU0_GPIO16 TX_CLK
GPIO73 INTn
MII0/MII1 GPIO85 MDIO0_MDIO
GPIO86 MDIO0_MDC
MII_RST# (IO Expander) RESET
MII1 PR0_PRU1_GPIO0 RXD0
PR0_PRU1_GPIO1 RXD1
PR0_PRU1_GPIO2 RXD2
PR0_PRU1_GPIO3 RXD3
PR0_PRU1_GPIO4 RX_DV
PR0_PRU1_GPIO5 RX_ER
PR0_PRU1_GPIO6 RX_CLK
PR0_PRU1_GPIO8 RX_LINK
PR0_PRU1_GPIO9 COL
PR0_PRU1_GPIO10 CRS
PR0_PRU1_GPIO11 TXD0
PR0_PRU1_GPIO12 TXD1
PR0_PRU1_GPIO13 TXD2
PR0_PRU1_GPIO14 TXD3
PR0_PRU1_GPIO15 TX_EN
PR0_PRU1_GPIO16 TX_CLK
GPIO119 INTn