SPRACM9B June   2019  – November 2020 TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Acronyms Used in This Document
  3. 2 Benefits of the TMS320F2838x MCU for High-Bandwidth Current Loop
  4. 3 Current Loops in Servo Drives
  5. 4 Outline of the Fast Current Loop Library
  6. 5 Fast Current Loop Evaluation
    1. 5.1 Evaluation Setup
      1. 5.1.1 Hardware
      2. 5.1.2 Software
      3. 5.1.3 FCL With T-Format Type Position Encoder
        1. 5.1.3.1 Connecting T-Format Encoder to IDDK
        2. 5.1.3.2 T-Format Interface Software
        3. 5.1.3.3 T-Format Encoder Latency Considerations
      4. 5.1.4 SDFM
      5. 5.1.5 Incremental System Build
  7. 6 Incremental Build Level 1
    1. 6.1 SVGEN Test
    2. 6.2 Testing SVGEN With DACs
    3. 6.3 Inverter Functionality Verification
  8. 7 Incremental Build Level 2
    1. 7.1 Setting the Overcurrent Limit in the Software
    2. 7.2 Current Sense Method
    3. 7.3 Voltage Sense Method
    4. 7.4 Setting Current Regulator Limits
    5. 7.5 Verification of Current Sense
    6. 7.6 Position Encoder Feedback
      1. 7.6.1 Speed Observer and Position Estimator
      2. 7.6.2 Verification of Position Encoder Orientation
  9. 8 Incremental Build Level 3
    1. 8.1 Observation One – PWM Update Latency
      1. 8.1.1 From the Expressions Window
      2. 8.1.2 From the Scope Plot
  10. 9 Incremental Build Level 4
    1. 9.1 Observation
  11. 10Incremental Build Level 5
  12. 11Incremental Build Level 6
    1. 11.1 Integrating SFRA Library
    2. 11.2 Initial Setup Before Starting SFRA
    3. 11.3 SFRA GUIs
    4. 11.4 Setting Up the GUIs to Connect to Target Platform
    5. 11.5 Running the SFRA GUIs
    6. 11.6 Influence of Current Feedback SNR
    7. 11.7 Inferences
      1. 11.7.1 Bandwidth Determination From Closed Loop Plot
      2. 11.7.2 Phase Margin Determination From Open Loop Plot
      3. 11.7.3 Maximum Modulation Index Determination From PWM Update Time
      4. 11.7.4 Voltage Decoupling in Current Loop
    8. 11.8 Phase Margin vs Gain Crossover Frequency
  13. 12Incremental Build Level 7
    1. 12.1 Run the Code on CPU1 to Allocate ECAT to CM
    2. 12.2 Run the Code on CM to Setup ECAT
    3. 12.3 Setup TwinCAT
    4. 12.4 Scanning for EtherCAT Devices via TwinCAT
    5. 12.5 Program ControlCard EEPROM for ESC
    6. 12.6 Running the Application
  14. 13Incremental Build Level 8
    1. 13.1 Run the Code on CPU1 to Allocate ECAT to CM
    2. 13.2 Run the Code on CM to Setup ECAT
    3. 13.3 Running the Application
  15. 14References
  16. 15Revision History

5.1.3.2 T-Format Interface Software

TI provides a software library and its source code to interface to T-format encoders, which is based off Configurable Logic Blocks (CLB) in the device. An user guide to help with the CLB tool, and application reports to help with Designing With The C2000 Configurable Logic Block and How to Migrate Custom Logic From an FPGA/CPLD to C2000 Microcontrollers are available online. They are also available in C2000ware (release 2_00_00_03 or later) at the following location

c:\ti\c2000\C2000Ware_<version>\utilities\clb_tool\clb_syscfg\doc

In the implementation of T-format interface, communication is achieved primarily by the integration of following components:

  • CPU
  • Configurable Logic Block (CLB)
  • Serial Peripheral Interface (SPI)
  • Device Interconnect (XBARs)

While SPI performs the encoder data transmit and receive functions, clock generation is controlled by CLB. The following functions are implemented inside the CLB module. Note that the CLB module can only be accessed via library functions provided in the PM tfomat Library and not otherwise configurable by users.

  • Ability to generate clock to the serial peripheral interface on chip and loop back to SPICLK input
  • Identification of the critical delay between the clock edges sent to the encoder and the received data
  • Ability to adjust the clock delay
  • Monitoring the data coming from encoder, via SPI Save In Master Out (SPISIMO), and poll for start pulse
  • Ability to measure the propagation delay at a specific interval as needed by the interface
  • Ability to configure the block and adjust delay the via software

Position information is received through SPI and is read through the SPI receive ISR spiRxFIFOISR() using readTformatEncPosition().

Detailed information about the T-format implementation on a launch pad platform is available at c:\ti\c2000\C2000Ware_MotorControl_SDK_2_01_00_00\libraries\position_sensing\tformat\Docs

The launch pad uses different GPIOs for T-format encoder interface as compared to IDDK. But for that, the core implementation is same. The list of GPIOs used on IDDK platform for cross reference are listed below:

#define  ENCODER_SPI_BASE    SPIB_BASE
#define  ENC_CLK_PWM_PIN     7 
#define  ENC_SPI_SIMO_PIN    24
#define  ENC_SPI_SOMI_PIN    25
#define  ENC_SPI_CLK_PIN     26
#define  ENC_SPI_STE_PIN     27
#define  ENC_TXEN_PIN        34
#define  ENC_PWREN_PIN       32