SPRACM9B June   2019  – November 2020 TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Acronyms Used in This Document
  3. 2 Benefits of the TMS320F2838x MCU for High-Bandwidth Current Loop
  4. 3 Current Loops in Servo Drives
  5. 4 Outline of the Fast Current Loop Library
  6. 5 Fast Current Loop Evaluation
    1. 5.1 Evaluation Setup
      1. 5.1.1 Hardware
      2. 5.1.2 Software
      3. 5.1.3 FCL With T-Format Type Position Encoder
        1. 5.1.3.1 Connecting T-Format Encoder to IDDK
        2. 5.1.3.2 T-Format Interface Software
        3. 5.1.3.3 T-Format Encoder Latency Considerations
      4. 5.1.4 SDFM
      5. 5.1.5 Incremental System Build
  7. 6 Incremental Build Level 1
    1. 6.1 SVGEN Test
    2. 6.2 Testing SVGEN With DACs
    3. 6.3 Inverter Functionality Verification
  8. 7 Incremental Build Level 2
    1. 7.1 Setting the Overcurrent Limit in the Software
    2. 7.2 Current Sense Method
    3. 7.3 Voltage Sense Method
    4. 7.4 Setting Current Regulator Limits
    5. 7.5 Verification of Current Sense
    6. 7.6 Position Encoder Feedback
      1. 7.6.1 Speed Observer and Position Estimator
      2. 7.6.2 Verification of Position Encoder Orientation
  9. 8 Incremental Build Level 3
    1. 8.1 Observation One – PWM Update Latency
      1. 8.1.1 From the Expressions Window
      2. 8.1.2 From the Scope Plot
  10. 9 Incremental Build Level 4
    1. 9.1 Observation
  11. 10Incremental Build Level 5
  12. 11Incremental Build Level 6
    1. 11.1 Integrating SFRA Library
    2. 11.2 Initial Setup Before Starting SFRA
    3. 11.3 SFRA GUIs
    4. 11.4 Setting Up the GUIs to Connect to Target Platform
    5. 11.5 Running the SFRA GUIs
    6. 11.6 Influence of Current Feedback SNR
    7. 11.7 Inferences
      1. 11.7.1 Bandwidth Determination From Closed Loop Plot
      2. 11.7.2 Phase Margin Determination From Open Loop Plot
      3. 11.7.3 Maximum Modulation Index Determination From PWM Update Time
      4. 11.7.4 Voltage Decoupling in Current Loop
    8. 11.8 Phase Margin vs Gain Crossover Frequency
  13. 12Incremental Build Level 7
    1. 12.1 Run the Code on CPU1 to Allocate ECAT to CM
    2. 12.2 Run the Code on CM to Setup ECAT
    3. 12.3 Setup TwinCAT
    4. 12.4 Scanning for EtherCAT Devices via TwinCAT
    5. 12.5 Program ControlCard EEPROM for ESC
    6. 12.6 Running the Application
  14. 13Incremental Build Level 8
    1. 13.1 Run the Code on CPU1 to Allocate ECAT to CM
    2. 13.2 Run the Code on CM to Setup ECAT
    3. 13.3 Running the Application
  15. 14References
  16. 15Revision History

11.1 Integrating SFRA Library

C2000™ Software Frequency Response Analyzer (SFRA) Library and Compensation Designer in SDK Framework describes the SFRA tool and guides you on how to integrate it into the C2000 platform can be found at:

C:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\Doc

The embedded firmware is available as a library in the DigitalPower SDK at:

C:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra

The SFRA GUIs are available as executable applications in the DigitalPower SDK at:

C:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\gui

Some example projects to understand SFRA are available at:

c:\ti\c2000\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\examples

In the ISR code, there are two functions that inject noise for SFRA and then collect the feedback data from the loop, they are:

  • injectSFRA()
  • collectSFRA()

The roles of these functions are self-explanatory from their names. They should be used in the sequence they are used in the code to collect the data in right sequence.

Note:
  • The disturbances due to analog signal path and quantization will impact the loop performance and hinder high bandwidth selections that can be verified using SFRA results. Therefore it is important to provide a current feedback with a higher SNR.
  • When evaluating current loops, if it is possible to hold the motor speed constant, it will help to minimize the impact of speed jitter related errors in the SFRA results. This is particularly useful when studying the Iq loop. If the voltage decoupling of current loop is good, then this requirement may not matter.

This tool provides the ability to study the D-axis or Q-axis current loops or the speed loop. The motor can be run at different speed/load conditions and at different bandwidths and the performance can be evaluated at each of these conditions. It can be seen that the controller can provide the designed bandwidth under all these conditions with a certain tolerance.

GUID-8ECBC336-8504-47D3-AF69-D3E62407E4D1-low.gifFigure 11-1 Level 6 Block Diagram

The implementation block diagram is given in Figure 11-1. The SFRA tool injects noise signal into the system at various frequencies and analyzes the system response and provides a Bode Plot of the actual physical system as seen during the test.