SPRACT2 August 2020 – MONTH AM67 , AM67 , AM67A , AM67A , AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA821U-Q1 , DRA821U-Q1 , DRA829J , DRA829J , DRA829J-Q1 , DRA829J-Q1 , DRA829V , DRA829V , DRA829V-Q1 , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM , TDA4VM-Q1 , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VP-Q1
Acronym | Description |
---|---|
Ref_clk | The internal clock of the OSPI controller. |
OSPI Clock | The clock of the OSPI bus. |
DQS |
Sometimes referred to as data strobe, this is a signal provided by some OSPI devices. It acts as a high speed clock for the data lanes. The controller can use a delayed DQS to sample incoming data. |
DLL |
Delay locked loop |
PDL | Programmable delay line |
OSPI PHY |
The part of the OSPI controller which sets up TX delay, and samples incoming data. |
Read Delay |
A parameter of the OSPI controller which determines which ref_clk cycle incoming data must be sampled in. |
Data Eye |
The period of time in which all data bits are valid. The sampling edge must occur inside the data eye for the byte to be read successfully. |
OTP | Optimal Tuning Point |