SPRZ455F December 2020 – February 2025 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
MMCSD: MMCSD1 and MMCSD2 Speed Issue
MMC1/2 data read and write operations fail at SDR104 (200 MHz SDR) due to timing issue on the output DAT and CMD path. This causes erroneous data to be transmitted out in SDR104 mode, and limits proper MMC1/2 data read and write operations to 100 MHz clock frequency.
Reduce clock frequency when performing data operations to 100 MHz for MMC1 and MMC2.