The frequency of the 32kHz crystal oscillator is set by properly dimensioning the load capacitors relative to the wanted load capacitance, CL, of the crystal. From the crystal, the two capacitors are placed in series. The PCB traces and the pads add some parasitic capacitance. Equation 1 shows how to calculate the total effective capacitance value.

The last simplification requires that C1 and C2 are equal.

The best way to measure the frequency accuracy of the oscillator is to output the 32kHz clock signal on an I/O pin. The frequency can be measured using a frequency counter without affecting the oscillator. The following code snippet outputs the selected 32kHz clock source to DIO19. Only one specific I/O can be used to output the 32kHz clock for CC23xx and CC27xx (see Table 6-1).

/* INCLUDES
*/
#include <ti/drivers/GPIO.h>
#include DeviceFamily_constructPath(inc/hw_types.h)
#include DeviceFamily_constructPath(inc/hw_memmap.h)
#include DeviceFamily_constructPath(inc/hw_ckmd.h)
#include DeviceFamily_constructPath(inc/hw_ioc.h)
#include DeviceFamily_constructPath(inc/hw_pmctl.h)
// ...
int main()
{
// ...

/** Add the following after Board_init();
* Be sure IOID used below is not used by any entries in PIN or
* GPIO tables from the board files.
* The clock source can be switched with constant clockSrc.
*/

uint8_t clockSrc = 0xF; // for LF crystal clock

// drive output low first
GPIO_setConfig(19, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_LOW);

// Configure the IOC.IOC19.PORTCFG MMR to select DTB
HWREG(IOC_BASE + IOC_O_IOC19) &= ~IOC_IOC19_PORTCFG_M;
HWREG(IOC_BASE + IOC_O_IOC19) |= IOC_IOC19_PORTCFG_DTB;

// Make sure the DTB mux selects in IOC (and if required in
// source clock IP) are reset that zero is driven on DTB0.
// ULLSEL mux select (select CKMD)
HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_ULLSEL_M;
HWREG(IOC_BASE + IOC_O_DTBCFG) |= 0x1 << IOC_DTBCFG_ULLSEL_S; // 0x1 to route CKMD to DTB0

// Enable IOC.DTBOE.EN0
HWREG(IOC_BASE + IOC_O_DTBOE) &= ~IOC_DTBOE_EN0_M;
HWREG(IOC_BASE + IOC_O_DTBOE) |= IOC_DTBOE_EN0_EN;

// select which clock (CKMD) to output on DTB0 (DTB[0])
HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_CLKSEL_M;
HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (clockSrc) << CKMD_DTBCTL_CLKSEL_S;

// enable DTB output
HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_EN_M;
HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN;

// ...
}