SWRA834 May   2025 CC2340R5 , CC2340R5-Q1 , CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Reference Designs
    1. 2.1 LP-EM-CC2340R53
    2. 2.2 LP-EM-CC2340R5
    3. 2.3 LP-EM-CC2340R5-Q1
    4. 2.4 LP-EM-CC2340R5-RGE-4x4-IS24
    5. 2.5 LP-EM-CC2745R10-Q1
  6. 3 Schematic
    1. 3.1 Schematic Overview
      1. 3.1.1 48MHz Crystal
      2. 3.1.2 32.768kHz Crystal
      3. 3.1.3 Filter
      4. 3.1.4 Decoupling Capacitors
      5. 3.1.5 Antenna Components
      6. 3.1.6 RF Shield
    2. 3.2 I/O Pins Drive Strength
    3. 3.3 Bootloader Pins
    4. 3.4 Serial Wire Debug (SWD) Pins
  7. 4 PCB Layout
    1. 4.1 Board Stack-Up
    2. 4.2 LC Filter
    3. 4.3 Decoupling Capacitors
    4. 4.4 Placement of Crystal Load Capacitors
    5. 4.5 Current Return Path
    6. 4.6 DC/DC Regulator
    7. 4.7 Antenna Matching Components
    8. 4.8 Transmission Lines
    9. 4.9 Electromagnetic Simulation
  8. 5 Antenna
  9. 6 Crystal Tuning
    1. 6.1 CC23xx and CC27xx Crystal Oscillators
    2. 6.2 Crystal Selection
    3. 6.3 Tuning the LF Crystal Oscillator
    4. 6.4 Tuning the HF Crystal Oscillator
  10. 7 Optimum Load Impedance
  11. 8 PA Table
  12. 9 Power Supply Configuration
    1. 9.1 Introduction to Power Supply
    2. 9.2 DC/DC Converter Mode
    3. 9.3 Global LDO Mode
  13. 10Board Bring-Up
    1. 10.1 Power On
    2. 10.2 RF Test: SmartRF Studio
    3. 10.3 RF Test: Conducted Measurements
      1. 10.3.1 Sensitivity
      2. 10.3.2 Output Power
    4. 10.4 Hardware Troubleshooting
      1. 10.4.1 No Link: RF Settings
      2. 10.4.2 No Link: Frequency Offset
      3. 10.4.3 Poor Link: Antenna
      4. 10.4.4 Bluetooth Low Energy: Device Does Advertising But Cannot Connect
      5. 10.4.5 Poor Sensitivity: Background Noise
      6. 10.4.6 High Sleep Power Consumption
  14. 11Summary
  15. 12References

4.4 Placement of Crystal Load Capacitors

The main oscillation loop current is flowing between the crystal and the load capacitors. Keep this signal path (crystal to CL1 to CL2 to crystal) as short as possible and use a symmetrical layout. Hence, both the ground connections of the capacitors need to always be as close as possible. Never route the ground connection between the capacitors or all around the crystal because this long ground trace is sensitive to crosstalk and EMI.