TIDUF63 December   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 PV or Battery Input With DC/DC Converter
    2. 1.2 Isolation and CLLLC Converter
    3. 1.3 DC/AC Converter
    4. 1.4 Key System Specifications
  8. 2System Design Theory
    1. 2.1 Boost Converter Design
    2. 2.2 MPPT Operation
    3. 2.3 CLLLC Converter Design
      1. 2.3.1 Achieving Zero Voltage Switching (ZVS)
      2. 2.3.2 Resonant Tank Design
    4. 2.4 DC/AC Converter Design
  9. 3System Overview
    1. 3.1 Block Diagram
    2. 3.2 Design Considerations
      1. 3.2.1 DC/DC Converter
        1. 3.2.1.1 Input Current and Voltage Senses and MPPT
        2. 3.2.1.2 Inrush Current Limit
      2. 3.2.2 CLLLC Converter
        1. 3.2.2.1 Low-Voltage Side
        2. 3.2.2.2 High-Voltage Side
      3. 3.2.3 DC/AC Converter
        1. 3.2.3.1 Active Components Selection
          1. 3.2.3.1.1 High-Frequency FETs: GaN FETs
          2. 3.2.3.1.2 Isolated Power Supply
          3. 3.2.3.1.3 Low-Frequency FETs
        2. 3.2.3.2 Passive Components Selection
          1. 3.2.3.2.1 Boost Inductor Selection
          2. 3.2.3.2.2 Cx Capacitance Selection
          3. 3.2.3.2.3 EMI Filter Design
          4. 3.2.3.2.4 DC-Link Output Capacitance
        3. 3.2.3.3 Voltage and Current Measurements
    3. 3.3 Highlighted Products
      1. 3.3.1  TMDSCNCD280039C - TMS320F280039C Evaluation Module C2000™ MCU controlCARD™
      2. 3.3.2  LMG3522R050 - 650-V 50-mΩ GaN FET With Integrated Driver
      3. 3.3.3  LMG2100R044 - 100-V, 35-A GaN Half-Bridge Power Stage
      4. 3.3.4  TMCS1123 - Precision Hall-Effect Current Sensor
      5. 3.3.5  AMC1302 - Precision, ±50-mV Input, Reinforced Isolated Amplifier
      6. 3.3.6  AMC3330 - Precision, ±1-V Input, Reinforced Isolated Amplifier With Integrated DC/DC Converter
      7. 3.3.7  AMC1311 - High-Impedance, 2-V Input, Reinforced Isolated Amplifier
      8. 3.3.8  ISO6741 - General-Purpose Reinforced Quad-Channel Digital Isolators with Robust EMC
      9. 3.3.9  UCC21540 - Reinforced Isolation Dual-Channel Gate Driver
      10. 3.3.10 LM5164 - 100-V Input, 1-A Synchronous Buck DC/DC Converter with Ultra-low IQ
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
      1. 4.2.1 DC/DC Board
      2. 4.2.2 DC/AC Board
    3. 4.3 Test Results
      1. 4.3.1 Input DC/DC Boost Results
      2. 4.3.2 CLLLC Results
      3. 4.3.3 DC/AC Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

3.2.2 CLLLC Converter

For this CLLLC converter, a transformer with a turn ratio of 4:11 and leakage inductance of 140 nH is used. The HV side has switching stage in half-bridge configuration with voltage doubler. All switches are based on GaN technology on both LV and HV sides.

To achieve ZVS, the effective parasitic capacitance was derived to calculate the needed magnetizing inductance. The parasitic capacitance of both sides (HV and LV) need to be considered.

The parasitic equivalent capacitance was calculated using the equation from Section 2.3.1:

Equation 16. C s ' = 2 × 0.26   n F × 11 4 2 = 3.9   n F
Equation 17. C E Q = 4 × 0.501   n F + 3.9   n F =   5.9   n F

Based on Equation 5, the maximum LM is 8.5 μH for 100-ns dead time. In this design LM = 6 μH was selected (Bourns 145449, D6735).

An additional energy check is required to provide ZVS. Energy stored in the calculated inductance needs to be higher than the energy stored in the COSS.

Equation 18. I M P E A K = 75 4 × 6 μ H + 0.14 μ H × 500 k H z = 6.1 A
Equation 19. 6 μ H + 0.14 μ H × ( 6.1 A ) 2 2   ≥   5.9 n F × 75 2 2
Equation 20. 114   μ J   ≥   16.6   μ J

Observe that the maximum magnetizing inductance is limited by a slew-rate requirement and not by an energy requirement.

This is a fixed frequency converter providing unit gain if operating at the resonance frequency. In this design, the leakage inductor of the transformer is 140 nH. A resonant capacitance of 660 nF was selected. The series resonant frequency can be calculated with Equation 9.

The resulting resonant frequency of the resonant tank is 523.6 kHz, which is very close to the desired value 500 kHz. To avoid parasitic effects, the converter is supposed to operate with a frequency slightly lower than the resonant one.

Figure 3-6 shows waveforms of the designed CLLLC converter transferring power from the LV to HV side. Ringing on the LV switching node is caused by parasitic current between the primary and secondary side. To reduce this ringing, increase the value of the resonant inductor.

GUID-20231129-SS0I-V4TT-VLMR-GPJ8RN41JKPF-low.png
C1 -LV side current, C2 - HV side SW node voltage, C3 - HV side current, C4 - LV side SW node voltage
Figure 3-6 CLLLC Converter Waveforms