TIDUFB1 December   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Control System Design Theory
        1. 2.2.1.1 PWM Modulation
        2. 2.2.1.2 Current Loop Model
        3. 2.2.1.3 DC Bus Regulation Loop
        4. 2.2.1.4 DC Voltage Balance Controller
    3. 2.3 Highlighted Products
      1. 2.3.1 TMS320F280013x
      2. 2.3.2 UCC5350
      3. 2.3.3 AMC1350
      4. 2.3.4 TMCS1123
      5. 2.3.5 UCC28750
      6. 2.3.6 LM25180
      7. 2.3.7 ISOTMP35
      8. 2.3.8 TLV76133
      9. 2.3.9 TLV9062
    4. 2.4 Hardware Design
      1. 2.4.1  Inductor Design
      2. 2.4.2  Bus Capacitor Selection
      3. 2.4.3  Input AC Voltage Sensing
      4. 2.4.4  Output DCBUS Voltage Sensing
      5. 2.4.5  Auxiliary Power Supply
      6. 2.4.6  Isolated Power Supply
      7. 2.4.7  Inductor Current Sensing
      8. 2.4.8  Gate Driver
      9. 2.4.9  Isolated Temperature Sensing
      10. 2.4.10 Overcurrent, Overvoltage Protection (CMPSS)
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Getting Started Hardware
        1. 3.1.1.1 Board Overview
        2. 3.1.1.2 Test Equipment
    2. 3.2 Software Requirements
      1. 3.2.1 Getting Started GUI
        1. 3.2.1.1 Test Setup
        2. 3.2.1.2 Overview of a GUI Software
        3. 3.2.1.3 Procedures of Test With GUI
      2. 3.2.2 Getting Started Firmware
        1. 3.2.2.1 Opening the Project Inside Code Composer Studio™
        2. 3.2.2.2 Project Structure
        3. 3.2.2.3 Test Setup
        4. 3.2.2.4 Running Project
          1. 3.2.2.4.1 INCR_BUILD 1: Open Loop
            1. 3.2.2.4.1.1 Setting, Building, and Loading the Project
            2. 3.2.2.4.1.2 Setup Debug Environment Windows
            3. 3.2.2.4.1.3 Using Real-Time Emulation
            4. 3.2.2.4.1.4 Running Code (Build 1)
          2. 3.2.2.4.2 INCR_BUILD 2: Closed Current Loop
            1. 3.2.2.4.2.1 Running Code (Build 2)
            2. 3.2.2.4.2.2 Building and Loading the Project and Setting Up Debug
          3. 3.2.2.4.3 INCR_BUILD 3: Closed Voltage and Current Loop
            1. 3.2.2.4.3.1 Building and Loading the Project and Setting Up Debug
            2. 3.2.2.4.3.2 Running Code (Build 3)
          4. 3.2.2.4.4 INCR_BUILD 4: Closed Balance, Voltage, and Current Loop
            1. 3.2.2.4.4.1 Building and Loading the Project and Setting Up Debug
            2. 3.2.2.4.4.2 Running Code (Build 4)
    3. 3.3 Test Results
      1. 3.3.1  IGBT Gate Rising and Falling Time
      2. 3.3.2  Power On Sequence
      3. 3.3.3  PFC Started by GUI
      4. 3.3.4  Zero Crossing Under 380VAC, 9kW
      5. 3.3.5  Current Ripple Under 380VAC,10kW
      6. 3.3.6  10kW Load Test With Grid Power
      7. 3.3.7  9kW Load Test With AC Power Source
      8. 3.3.8  Power Analyzer Results
      9. 3.3.9  Thermal Performance
      10. 3.3.10 Voltage Short Interrupt Test
      11. 3.3.11 Efficiency, iTHD, and Power Factor Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 Bill of Material (BOM)
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.4.2 Bus Capacitor Selection

The bus capacitor is responsible for removing the ripple on the DC voltage that can be caused by the draw of sinusoidal currents. The capacitor value and the DC bus ripple are related by Equation 12.

Equation 12. C = 1 3 P a c 4 × f × V 2 - V - ∆ V 2

This equation is used to select the minimum DC bus capacitance value.

Note:

The calculation in Equation 12 can yield to an over design of the capacitor. The capacitor sizing is more dependent on the load and the nature of current drawn. For three-phase PFC the power ripple is fairly small as the input always has a path to the output. Only use Equation 12 for reference and be aware that this yields to over design.