TIDUFB1 December 2024
The board is run in an open-loop mode with a
fixed-duty cycle. The duty cycle is controlled with the dutyPU_DC variable.
This build verifies the sensing of feedback values from the power stage and also the
operation of the PWM gate driver, which makes sure there are no hardware issues.
Additionally, calibration of input and output voltage sensing can be performed in this
build. The software structure for this build is shown in Figure 3-7. Blocks that run in the slower ISR are marked. Other blocks are run in the fast
controlISR.
Figure 3-7 Build Level 1 Control Software Diagram: Open Loop Project